AS7C34096A

February 2004 e e hAS7C34096 Pin compatible to S Industrial and commercial temperature a 524,288 words × 8 bits t Organization: a and ground pins Center power D .speed High w w w Low power consumption: ACTIVE Features - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time - 650 mW / max @ 10 ns - 18 mW / max CMOS U 4 t .c om AS7C34096A ® 3.3V 512K × 8 CMOS SRAM Equal access and cycle times Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 - 48 pin BGA. 6 X 9mm Pin arrangements A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA 36-pin SOJ (400 mil) NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC Low power consumption: STANDBY Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1 Row decoder 524,288 × 8 Array (4,194,304) Sense amp Column decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 w Selection guide w w .D Control Circuit t a I/O8 S a e h A B C D E F G H t e 1 U 4 2 A1 A2 NC NC NC NC OE A10 .c NC NC A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 NC NC m o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-pin TSOP 2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC N...