GL2L5MS150D

w w w .D at h S a t e e 4U . m o c D elay L ine D ata B ook CH1 S 21 l og M AG 5 dB/ R EF 0 dB 2. 931 G H z M AR KER 1 2. 931 G H z 1 CH2 S 11 l og M AG M AR KER 2 0. 949 G H z w w w .D t a 2 S a 10 dB/ e h t e 1 2. 997 dB U 4 .c m o R EF 0 dB 2 15. 000 dB . 949 G H z STAR T . 050 G H z STO P 6. 000 G H z w w w .D at h S a t e e 4U . m o c T hin F ilm T echnology. D elay L ines. Because Timing is Everything. tm T ABLE of C ONTENTS Contents............................................................................................. 2 Introduction........................................................................................3 Definitions..........................................................................................4 Delay Line Test Methods...................................................................5 High Frequency Delay Lines Single In Line DL1 Series.....................................................6-7 Surface Mount GL1 Series....................................................8-9 Surface Mount GL2 Differential Series.............................10-11 Intermediate Frequency Delay Lines Single In Line DS1 Series..................................................12-13 Chip Delay Line CL Series..............................................................14 Bandwith Considerations.................................................................15 Complimentary Products Positive Emitter Coupled Logic (PECL) Te...