(CY7C006AV - CY7C145AV) Dual Port Static RAM
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Stati...
Description
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
Features
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True Dual-Ported memory cells which allow simultaneous access of the same memory location 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) 0.35-micron CMOS for optimum speed/power High-speed access: 20/25 ns Low operating power — Active: ICC = 115 mA (typical)
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CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
Fully asynchronous operation Automatic power-down Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flag for port-to-port communication Pin select for Master or Slave Commercial and Industrial Temperature Ranges Available in 68-pin PLCC (all) and 64-pin TQFP (7C006AV & 7C144AV)
— Standby: ISB3 = 10 µA (typical)
Logic Block Diagram
R/WL CEL OEL
[1]
8/9
I/O0L–I/O7/8L
A0L–A11–14L
[2]
12–15
A0L–A11–14L CEL OEL R/WL SEML BUSYL INTL
[3]
[2]
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Address Decode
12–15
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t a
I/O Control
S a
e h
t e
U 4
.c
m o
R/WR CER OER
8/9
[1]
I/O Control
I/O0R–I/O7/8R
True Dual-Ported RAM Array
Address Decode
12–15
12–15
[2]
A0R–A11–14R
Interrupt Semaphore Arbitration
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