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Description Features
HM51W16165 Series HM51W18165 Series
16 M EDO DRAM (1-Mword × 16-bit) 4 k Refresh/1 k Refresh
The HM51W16165 Series, HM51W18165 Series are CMOS dynamic RAMs organized as 1,048,576-word × 16-bit. They employ the most advanced CMOS technology for high performance and low power. HM51W16165 Series, HM51W18165 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have package variations of standard 400-mil 42-pin plastic SOJ and 400-mil 50-pin plastic TSOP.
• Single 3.3 V (±0.3 V) • Access time: 50 ns/60 ns/70 ns (max) • Power dissipation Active mode : 396 mW/360mW/324 mW (max) (HM51W16165 Series) : 684 mW /612 mW /540 mW (max) (HM51W18165 Series) Standby mode : 7.2 mW (max) : 0.54 mW (max) (L-version) • EDO page mode capability • Refresh cycles 4096 refresh cycles : 64 ms (HM51W16165 Series) : 128 ms (L-version) 1024 refresh cycles : 16 ms (HM51W18165 Series) : 128 ms (L-version) • 4 variations of refresh RAS -only refresh CAS -before-RAS refresh Hidden refresh Self refresh (L-version) • 2CAS-byte control
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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E0153H10 (Ver. 1.0) (Previous ADE-203-650D (Z)) Jul. 6, 2001 (K)
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HM51W16165 Series, HM51W18165 Series
• Battery backup operation (L-version)
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Type No. HM51W16165J-5 HM51W16165J-6 HM51W16165J-7 HM51W16165LJ-5 HM51W16165LJ-6 HM51W16165LJ-7 HM51W18165J-5 HM51W18165J-6 HM51W18165J-7 HM51W18165LJ-5 HM51W18165LJ-6 HM51W18165LJ-7 HM51W16165TT-5 HM51W16165TT-6 HM51W16165TT-7 HM51W18165TT-5 HM51W18165TT-6 HM51W18165TT-7 2
Ordering Information
Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns Package 400-mil 42-pin plastic SOJ (CP-42D)
HM51W16165LTT-5 HM51W16165LTT-6 HM51W16165LTT-7
HM51W18165LTT-5 HM51W18165LTT-6 HM51W18165LTT-7
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Data Sheet E0153H10
400-mil 50-pin plastic TSOP II (TTP-50/44DC)
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HM51W16165 Series, HM51W18165 Series
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VCC I/O0 I/O1 I/O2 I/O3 V CC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin Arrangement
HM51W16165J/LJ Series 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 HM51W16165TT/LTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Description
Pin name A0 to A11 Function Address input — Row/Refresh address A0 to A11 — Column address A0 to A7 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
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(Top view) Data Sheet E0153H10
NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25 (Top view)
36 35 34 33 32 31 30 29 28 27 26
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
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I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
HM51W16165 Series, HM51W18165 Series
Pin Arrangement
HM51W18165J/LJ Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V
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VCC I/O0 I/O1 I/O2 I/O3 V CC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
HM51W18165TT/LTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Pin Description
Pin name A0 to A9 Function Address input — Row/Refresh address A0 to A9 — Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
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(Top view)
NC NC WE RAS NC NC A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25 (Top view)
36 35 34 33 32 31 30 29 28 27 26
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
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I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
Data Sheet E0153H10 4
HM51W16165 Series, HM51W18165 Series
Row decoder
Row decoder
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A0 A1 to A7 A8 A9 A10 A11
Block Diagram (HM51W16165 Series)
RAS UCAS LCAS WE OE
Timing and control
Column decoder 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array
Block Diagram(HM51W18165 Series)
RAS
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Column buffers • • • address • • • Row address buffers
I/O buffers
I/O0 to I/O15
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UCAS LCAS 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array
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Timing and control
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I/O buffers
A0 A1 to A9 • • • Column address buffers
Column decoder
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I/O0 to I/O15
• • •
Row address buffers
Data Sheet E0153H10 5
HM51W16165 Series, HM51W18165 Series
Truth Table
RAS H L L L L L L L L L L L L.