AS7C513B

March 2004 AS7C513B ® 5V 32K×16 CMOS SRAM Features Industrial and commercial temperature Organization: 32,768 words × 16 bits Center power and ground pins High speed 10/12/15/20 ns address access time 5, 6, 7, 8 ns output enable access time Low power consumption: ACTIVE 605mW / max @ 10 ns Low power consumption: STANDBY 55 mW / max CMOS I/O 6T 0.18u CMOS Technology Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O 44-pin JEDEC standard package 400 mil SOJ 400 mil TSOP 2 ESD protection > 2000 volts Latch-up current > 200 mA Logic block diagram A0 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 Pin arrangement VCC Row decoder A1 32K × 16 Array GND I/O buffer Control circuit Column decoder A8 A9 A10 A12 A13 A11 WE UB OE LB CE Selection guide w w .D w t a A14 S a AS7C513B e h t e U 4 NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC .c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 m o 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-Pin SOJ, TSOP 2 (400 mil) A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC -10 10 5 110 10 -12 12 6 100 10 -15 15 7 90 10 -20 20 8 80 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 3/26/04, v.1.3 Alliance Semiconductor w w w .D at h S a 10 t e e 4U m o .c Unit ns ns mA mA P. 1 of 9 Co...