W134M Datasheet: (W134M/S) Direct Rambus Clock Generator





W134M (W134M/S) Direct Rambus Clock Generator Datasheet

Part Number W134M
Description (W134M/S) Direct Rambus Clock Generator
Manufacture Cypress Semiconductor
Total Page 12 Pages
PDF Download Download W134M Datasheet PDF

Features: W134M/W134S Direct Rambus™ Clock Gene rator Features • Differential clock s ource for Direct Rambus™ memory subsy stem for up to 800-MHz data transfer ra te • Provide synchronization flexibil ity: the Rambus® Channel can optionall y be synchronous to an external system or processor clock • Power-managed ou tput allows Rambus Channel clock to be turned off to minimize power consumptio n for mobile applications • Works wit h Cypress CY2210, W133, W158, W159, W16 1, and W167 to support Intel® architec ture platforms • Low-power CMOS desig n packaged in a 24-pin QSOP (150-mil SS OP) package Description The Cypress W1 34M/W134S provides the differential clo ck signals for a Direct Rambus memory s ubsystem. It includes signals to synchr onize the Direct Rambus Channel clock t o an external system clock but can also be used in systems that do not require synchronization of the Rambus clock. Block Diagram REFCLK MULT0:1 Pin Confi guration PLL PCLKM SYNCLKN Phase Alignment Output Logic w S0:1 STOPB w w.

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W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory The Cypress W134M/W134S provides the differential clock
subsystem for up to 800-MHz data transfer rate
signals for a Direct Rambus memory subsystem. It includes
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mmobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
oand W167 to support Intel® architecture platforms
.c• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
t4UBlock Diagram
eREFCLK
eMULT0:1
PLL
taShPCLKM
.DaSYNCLKN
Phase
Alignment
Output
Logic
CLK
CLKB
Pin Configuration
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 VDD
21 GND
20 CLK
19 NC
18 CLKB
17 GND
16 VDD
15 MULT0
14 MULT1
13 GND
www .comS0:1
t4USTOPB
Test
Logic
ww.DataSheeCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-07426 Rev. *C
Revised June 1, 2005

                    
              






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