DP83840A

DP83840A 10/100 Mb/s Ethernet Physical Layer March 1997 DP83840A 10/100 Mb/s Ethernet Physical Layer General Description The DP83840A is a Physical Layer device for Ethernet 10BASE-T and 100BASE-X using category 5 Unshielded, Type 1 Shielded and Fiber Optic cables. This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces to the PMD sublayer through National Semiconductor's DP83223 Twisted Pair Transceiver, and to the MAC layer through a Media Independent Interface (MII), ensuring interoperability between products from different vendors. The DP83840A is designed with National Semiconductor's BiCMOS process. Its system architecture is based on the integration of several of National Semiconductor's industry proven core technologies: 10BASE-T ENDEC/Transceiver module to provide the 10 Mb/s IEEE 802.3 functions Clock Recovery/Generator Modules from National Semiconductor's leading FDDI product FDDI Stream Cipher (Cyclone) 100BASE-X physical coding sub-layer (PCS) and control logic that integrate the core modules into a dual speed Ethernet physical layer controller Features IEEE 802.3 10BASE-T compatible--ENDEC and UTP/ STP transceivers and filters built-in IEEE 802.3u 100BASE-X compatible--support for 2 pair Category 5 UTP (100m), Type 1 STP and Fiber Optic Transceivers--Connects directly to the DP83223 Twisted Pair Transceiver ANSI X3T12 TP-PMD compatible IEEE 802.3u Auto-Negotiation for automatic speed selection IEEE 802.3...