MPC2005

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2004/D Advance Information 256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits. Bursts can be initiated with the SRAMADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the SRAMCNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in–depth description of the cache module. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. These cache modules are plug and pin compatible with the MPC2006, a 1MB synchronous module also designed for the PReP and CHRP specifications. They are also co...