MT88L89 Micro Interface Datasheet

MT88L89 Datasheet, PDF, Equivalent


Part Number

MT88L89

Description

3V Integrated DTMFTransceiver with Adaptive Micro Interface

Manufacture

Mitel Networks Corporation

Total Page 20 Pages
Datasheet
Download MT88L89 Datasheet


MT88L89
® MT88L89
3V Integrated DTMF Transceiver
Advance Information with Adaptive Micro Interface
Features
ISSUE 1
May 1995
• Central office quality DTMF transmitter/
receiver
Ordering Information
MT88L89AE
20 Pin Plastic DIP
• Low voltage operation (2.7-3.6V)
MT88L89AC
20 Pin Ceramic DIP
• Adjustable guard time
MT88L89AS
20 Pin SOIC
• Automatic tone burst mode
• Call progress tone detection to -30dBm
m• Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
o• DTMF transmitter/receiver power down via
.cregister control
Applications
U• Credit card systems
t4• Paging systems
• Repeater systems/mobile radio
e• Interconnect dialers
e• Personal computers
hDescription
SThe MT88L89 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
tatechnology offering low power consumption and high
reliability.
MT88L89AN
24 Pin SSOP
MT88L89AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features. The transmitter and receiver may
independently be powered down via register control.
.DaTONE
D/A
Converters
www omIN+
.cIN-
t4UGS
eOSC1
taSheOSC2
Tone Burst
Gating Cct.
+ Dial
- Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
www.DaVDD VRef VSS
ESt St/GT
Figure 1 - Functional Block Diagram
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
4-125

MT88L89
MT88L89
Advance Information
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
20 VDD
19 St/GT
18 ESt
17 D3
16 D2
15 D1
14 D0
13 IRQ/CP
12 DS/RD
11 RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
24 PIN SSOP
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
NC 5
25 NC
VRef 6
24 NC
VSS 7
23 NC
OSC1 8
22 D3
OSC2 9
21 D2
NC 10
20 D1
NC 11
19 D0
28 PIN PLCC
Pin Description
Figure 2 - Pin Connections
Pin #
20 24 28 Name
Description
1 1 1 IN+ Non-inverting op-amp input.
2 2 2 IN- Inverting op-amp input.
334
GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4 4 6 VRef Reference Voltage output (VDD/2).
5 5 7 VSS Ground (0V).
6 6 8 OSC1 Oscillator input. This pin can also be driven directly by an external clock.
7 7 9 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8 10 12 TONE Output from internal DTMF transmitter.
9 11 13 R/W (Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
(WR)
10 12 14
CS Chip Select input. This signal must be qualified externally by either address strobe
(AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
11 13 15 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is
only required when the device is being accessed. TTL compatible.
13 15 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter, see Figure 8.
14- 18- 19- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
17 21 22
(Intel). TTL compatible.
18 22 26
19 23 27
ESt
St/GT
Early Steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected
at St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage
on St.
4-126


Features ® MT88L89 3V Integrated DTMF Transcei ver Advance Information with Adaptive M icro Interface Features • • • • • • Central office quality DT MF transmitter/ receiver Low voltage op eration (2.7-3.6V) Adjustable guard tim e Automatic tone burst mode Call progre ss tone detection to -30dBm ISSUE 1 M ay 1995 Adaptive micro interface enabl es compatibility with existing MT8880/M T8888 designs DTMF transmitter/receiver power down via register control Appli cations • • • • • Credit car d systems Paging systems Repeater syst ems/mobile radio Interconnect dialers P ersonal computers Description The MT8 8L89 is a monolithic DTMF transceiver w ith call progress filter. It is fabrica ted in CMOS technology offering low pow er consumption and high reliability. T ONE IN+ INGS OSC1 OSC2 + - m o .c U 4 t e e h S a t a .D w w w ∑ D/A Conv erters Row and Column Counters Transmit Data Register Status Register Data Bus Buffer Tone Burst Gating Cct. Dial Tone Filter Control Logic Interrupt Logic High Group F.
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