Document
128Mb: x16, x32 MOBILE SDRAM
SYNCHRONOUS DRAM
Features
• Temperature Compensated Self Refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes • Self Refresh Mode; standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Partial Array Self Refresh power-saving mode
MT48LC8M16LFF4, MT48V8M16LFF4, MT48LC8M16TG, MT48V8M16TG, MT48V8M16P, MT48LC4M32LFF5, MT48V4M32LFF5
Table 1:
Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
Configurations
8 MEG X 16 2 Meg x 16 x 4 banks 4K 4K (A0–A11)
Options
• VDD/VDDQ 3.3V/3.3V 2.5V/2.5V – 1.8V • Configurations 8 Meg x 16 (2 Meg x 16 x 4 banks) 4 Meg x 32 (1 Meg x 32 x 4 banks) • Package/Ball out 54-ball VFBGA (8mm x 8mm)1 54-ball VFBGA (8mm x 8mm)1 Lead-Free 90-ball VFBGA (8mm x 13mm)2 90-ball VFBGA (8mm x 13mm)2 Lead-Free 54-Pin TSOP II (400 mil) 54-Pin TSOP II (400 mil) Lead-Free • Timing (Cycle Time) 7.5ns @ CL = 3 (133 MHz) 8ns @ CL = 3 (125 MHz) 10ns @ CL = 3 (100 MHz) • Temperature Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Extended (-25°C to +75°C)
Marking
LC V
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8M16 4M32 F4 B4 F5 B5 TG P
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-75M -8 -10 -75M -8 -10 -8 -10
Table 2:
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4 (BA0, BA1) 512 (A0–A8)
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4 MEG X 32
1 Meg x 32 x 4 banks 4K 4K (A0–A11) 4 (BA0, BA1) 256 (A0–A7)
Key Timing Parameters
CL = CAS (READ) latency ACCESS TIME SPEED CLOCK GRADE FREQUENCY CL = 1 CL = 2 CL = 3 tRCD 133MHz 125 MHz 100 MHz 100MHz 100 MHz 83 MHz 50 MHz 40 MHz – – – – 19ns 22ns – – 6 8ns 8ns – – 5.4 7ns 7ns – – – – 19ns 20ns 20ns 19ns 20ns 20ns 20ns 20ns
tRP
19ns 20ns 20ns 19ns 20ns 20ns 20ns 20ns
-75M -8 -10 None IT XT
Part Number Example:
MT48V8M16LFB5-8
NOTE:
1. x16 only. 2. x32 only.
09005aef8071a76b 128Mbx16x32Mobile_1.fm - Rev. J 7/04 EN
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©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 MOBILE SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Ini.