29C010 and EROM Datasheet

29C010 Datasheet, PDF, Equivalent


Part Number

29C010

Description

High Speed CMOS 1M Programmable and EROM

Manufacture

Turbo IC

Total Page 8 Pages
Datasheet
Download 29C010 Datasheet


29C010
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
HIGH SPEED CMOS
1 Megabit PROGRAMMABLE and ERASABLE ROM
128K X 8 BIT FLASH PEROM
FEATURES:
DESCRIPTION:
120 ns Access Time
5 Volt Only Reprogramming
The Turbo IC 29C010 is a 128K x 8 Flash programmable
Sector Program Operation
and erasable read only memory (PEROM) fabricated with
Single Cycle Reprogram (Erase & Program)
Turbo IC’s proprietary, high reliability, high performance
m1024 Sectors (128 bytes/sector)
CMOS technology. Its 1024K bits of memory are organized
oInternal Address and Data Latches for 128 Bytes as 128K by 8 bits. The device offers access time of 120 ns
Automatic Sector Programming Operation
with power dissipation below 330 mW.
.cInternal Control Timer
Fast Program Times
The 29C010 has a 128 bytes sector program operation en-
Page Program Cycles: 10 ms Typical
abling the entire memory to be programmed typically in less
UTime to Rewrite Complete Memory: 10 s
than 10 seconds. During a program operation, the address
t4Typical Byte Program Cycle Time: 80 µs
and a complete sector (128 bytes) of data are internally
Software Data Protection
latched, freeing the address and data bus for other micro-
Low Power Dissipation
processor operations. The programming process is auto-
e60 mA Active Current
matically controlled by the device using an internal control
e100 µA CMOS Standby Current
timer. Data polling on I/O7 or a Toggle bit can be used to
Direct Microprocessor End of Program Detection
detect the end of a programming cycle. In addition, the
hData Polling
29C010 includes an user-optional software data write mode
High Reliability CMOS Technology
offering additional protection against unwanted (false) write.
SEndurance: 10,000 Cycles
Data Retention: 10 years
The 29C010 does not require a separate high voltage to
taCMOS and TTL Compatible Inputs and Outputs
program the device. 5 volts is all that is required.
Single 5V ± 10% Power Supply for Read and Program-
aming Operations
JEDEC Approved Byte Pinout
w.DPIN CONFIGURATIONS:
wA12 A16 VCC NC
w mA15 NC WE
.coA7 5 4 3 2 1 32 313029 A14
A6 6
28 A13
A5 7
27 A8
UA4 8
26 A9
t4A3 9
25 A11
A2 10
24 OE
eA1 11
23 A10
eA0 12
22 CE
hI/O0
13 21
14 15 16 17 18 19 20
I/O7
SI/O1 GND I/O4 I/O6
taI/O2 I/O3 I/O5
www.Da32 pins PLCC
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
32 pins PDIP
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 pins TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3

29C010
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
PIN DESCRIPTION
ADDRESSES (A0 - A16)
The Addresses are used to select an 8 bits memory location during a
program or read operation.
CHIP ENABLE (CE)
The Chip Enable input must be low to enable all read/program operations
on the device. By setting CE high, the device is disabled and the power
consumption is extremely low with the standby current below 100 µA.
OUTPUT ENABLE (OE)
The Output Enable input activates the output buffers during the read op-
erations.
WRITE ENABLE (WE)
The Write Enable input initiates the programming of data into the memory.
DATA INPUT/OUTPUT (I/O0-I/O7)
Data Input/Output pins are used to read data out of the memory or to
program Data into the memory.
DEVICE OPERATION
READ
TOGGLE BIT
The 29C010 is accessed like a static RAM. Read operations are initiated
by both CE and OE on low and terminated by either CE or OE returning
high. The outputs are at the high impedance state whenever CE or OE
returns high. The two line control architecture gives designers flexibility in
preventing bus contention.
PROGRAM
A program cycle is initiated when CE and WE are low and OE is high. The
address is latched internally on the falling edge of the CE or WE, which-
ever occurs last. The data is latched by the rising edge of CE or WE,
whichever occurs first. Once a programming cycle has been started, the
internal timer automatically generates the program sequence to the comple-
tion of the program operation.
SECTOR PROGRAM OPERATION
In addition to DATA Polling the 29C010 provides another method for deter-
mining the end of a programming or erase cycle. During a program
or erase operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining
the toggle bit may begin at any time during a program cycle.
CHIP CLEAR
The content of the entire memory array of the 29C010 may be altered to
HIGH by the use of the CHIP CLEAR operation. By setting CE to low, OE
to 12 Volts, and WE to low, the entire memory array can be cleared (written
HIGH) within 20 ms.The CHIP CLEAR operation is a latch operation mode.
After CE, WE, and OE get the CHIP CLEAR process started, the internal
chip timer takes over the CHIP CLEAR operation and CE, OE, or WE
becomes free to be used by the system for other purposes.
The device is reprogrammed on a sector basis. When a byte of data within
a sector is to be changed, data for the entire sector must be loaded into the
device. Any byte that is not loaded during the programming of its sector will
be erased to read FFh. The programming operation of the 29C010 allows
128 bytes of data to be serially loaded into the device and then simulta-
neously written into memory during the internally generated program cycle.
After the first byte has been loaded, successive bytes of data must be
loaded until the full sector of 128 bytes is loaded. Each new byte to be
written must be loaded within 300 µs of the previously loaded byte. The
sector address defined by the addresses A7 - A16 is latched by the first
CE or WE falling edge which initiates a program cycle and they stay latched
until the completion of the program cycle. Any changes in the sector ad-
dresses during the load-program cycle will not affect the initially latched
sector address. Addresses A0 - A6 are used to define which bytes will be
loaded within the 128 bytes sector. The bytes may be loaded in any order
that is convenient to the user. The content of a loaded byte may be altered
at any time during the loading cycle if the maximum allowed byte-load time
(300 µs) is not exceeded. All the 128 bytes of the page are serially loaded
and are programmed in a single 10 ms program cycle
DATA POLLING
The 29C010 features DATA Polling to indicate the completion of a program
cycle to the host system. During a program cycle, an attempted read of the
last byte loaded into the page will result in the complement of the loaded
byte on I/O7, i.e., loaded 0 would be read 1. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may
be started. DATA Polling may begin at any time during the programming
cycle.
HARDWARE DATA PROTECTION
The 29C010 has three hardware features to protect the written content of
the memory against inadvertent programming:
a) Vcc threshold detector - If Vcc is below 3 V the program capabilities of
the chip is inhibited for whatever input conditions.
b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is
not able to initiate a program cycle.
c) Write inhibit - Holding OE at low, or CE at high, or WE at high inhibits the
program cycle.
SOFTWARE DATA PROTECTION
The 29C010 offers a software controlled data program protection feature.
The device is delivered to the user with the software data protection DIS-
ABLED, i.e., the device will go to the program operation as long as Vcc
exceeds 3 V and CE, WE, and OE inputs are set at program mode levels.
The 29C010 can be automatically protected against an accidental write
operation during power-up or power-down without any external circuitry by
enabling the software data protection feature. This feature is enable after
the first program cycle which includes the software algorithm. After this
operation is done the program function of the device may be performed
only if every program cycle is preceded by the software algorithm. The
device will maintain its software protect feature for the rest of its life, unless
the software algorithm for disabling the protection is implemented.
www.DataSheet4U.com


Features Turbo IC, Inc. 29C010 ADVANCE INFORMATIO N HIGH SPEED CMOS 1 Megabit PROGRAMMAB LE and ERASABLE ROM 128K X 8 BIT FLASH PEROM FEATURES: • 120 ns Access Time • 5 Volt Only Reprogramming • Secto r Program Operation Single Cycle Reprog ram (Erase & Program) 1024 Sectors (128 bytes/sector) Internal Address and Dat a Latches for 128 Bytes • Automatic S ector Programming Operation Internal Co ntrol Timer • Fast Program Times Page Program Cycles: 10 ms Typical Time to Rewrite Complete Memory: 10 s Typical B yte Program Cycle Time: 80 µs • Soft ware Data Protection • Low Power Diss ipation 60 mA Active Current 100 µA CM OS Standby Current • Direct Microproc essor End of Program Detection Data Pol ling • High Reliability CMOS Technolo gy Endurance: 10,000 Cycles Data Retent ion: 10 years • CMOS and TTL Compatib le Inputs and Outputs • Single 5V ± 10% Power Supply for Read and Programmi ng Operations • JEDEC Approved Byte P inout DESCRIPTION: The Turbo IC 29C010 is a 128K x 8 Flash programmable and erasable read .
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