TM50S116T

TMC Description TM50S116T SDRAM The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features n Package 400-mil 50-pin TSOP(II) n JEDEC PC133/PC100 compatible n Single 3.3V Power Supply n LVTTL Signal Compatible n Byte control(DQML and DQMU) n Auto and Self Refresh n 64ms refresh period (4K cycles) n 11-Row x 8-Column organization n 2-Bank operation controlled by BA0 n Programmable n Pin33 and 37 are “No Connected” - CAS Latency (3 or 2 clocks) n Fully synchronous operation referenced - Burst Length (1,2,4,8 & full page) to clock rising edge - Burst type (Sequential & Interleave) n Burst read/write and burst read/single write operations capability Frequency vs. AC Parameter Symbol tCK fCK tAC trcd Parameter Min. clock cycle time @CL=3 Max. operating frequency @CL=3 Max. access time from CLK @CL=3 Min. row to column delay -6 6 166.7 5.0 18 -7 7 143 5.4 18 - 75 7.5 133.3 5.4 20 Unit ns Mhz ns ns www.DataSheet4U.com For reference only. 1 TMC Rev:1.0 www.DataSheet4U.com TMC Pin Description Pin Name CLK CKE /CS /RAS /CAS /WE DQ0~DQ15 Function Master Clock Clock Enable Chip Select Row A...