K3N4C1000D-DC

K3N4C1000D-D(G)C 8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM FEATURES Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode) Fast access time : 100ns(Max.) Supply voltage : single +5V Current consumption Operating : 50mA(Max.) Standby : 50µA(Max.) Fully static operation All inputs and outputs TTL compatible Three state outputs Package -. K3N4C1000D-DC : 42-DIP-600 -. K3N4C1000D-GC : 44-SOP-600 CMOS MASK ROM GENERAL DESCRIPTION The K3N4C1000D-D(G)C is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x16 bit(word mode) depending on BHE voltage level. (See mode selection table) This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3N4C1000D-DC is packaged in a 42-DIP and the K3N4C1000D-GC in a 44-SOP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A18 . . . . . . . . A0 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (524,288x16/ 1,048,576x8) A18 A17 A7 A6 A5 1 2 3 4 5 6 7 8 9 42 N.C 41 A8 40 A9 39 A10 38 A11 37 A12 36 A13 35 A14 34 A15 33 A16 32 BHE 31 VSS 30 Q15/A-1 29 Q7 28 Q14 27 Q6 26 Q13 25 Q5 24 Q12 23 Q4 22 VCC N.C 1 A18 A17 A7 A6 A5 A4 A3 A2 2 3 4 5 6 7 8 9 44 N.C 43 N.C 42 A8 41 ...