Identification EEPROM. 24RF08C Datasheet

24RF08C EEPROM. Datasheet pdf. Equivalent

24RF08C Datasheet
Recommendation 24RF08C Datasheet
Part 24RF08C
Description Asset Identification EEPROM
Feature 24RF08C; .
Manufacture ATMEL Corporation
Download 24RF08C Datasheet

ATMEL Corporation 24RF08C
Dual-port Nonvolatile Memory - RFID and Serial Interfaces
Two-wire Serial Interface:
– Compatible with a Standard AT24C08 Serial EEPROM
– Programmable Access Protection to Limit Reads or Writes from Either Port
– Lock/Unlock Function, Coil Connection Detection
RFID Interface:
125 kHz Carrier Frequency for Long Range Access
2-Wire Connection to External Coil Antenna and Tuning Capacitor
Multi-tag Management to Handle Several Tags in the Field at Once
12 RFID Commands for Tag Control and Memory Read/Write
ID Write and Lock from RFID Port
Ultra Low Power Single Bit Write - 25 µA
Highly-reliable EEPROM Memory
8K bits (1K bytes), Organized as 8 Blocks of 128 Bytes Each
16-byte Page Write, 10 ms Write Time
10 Years Retention, 100K Write Cycle Endurance
-40°C to +85°C Operation, 2.4V to 5.5V Supply, 8-Lead JEDEC SOIC Package
The AT24RF08C functions as a dual access EEPROM, with both a wired serial port
and a wireless RFID port used to access the memory. Access permissions are set
from the serial interface side to isolate blocks of memory from improper access. The
RFID interface can be powered solely from the attached coil permitting remote reads
and writes of the device when VCC is not applied.
Block Diagram
Pin Configurations
Pin Name
L1 Coil Connection
L2 Coil Connection
Protection Input
Serial Data,Open Drain I/O
SCL Serial Clock Input
WP Write Protect Input
Supply: 2.4V - 5.5V
8-Pin SOIC
7 WP
Rev. 1072E09/99

ATMEL Corporation 24RF08C
General Overview
The AT24RF08C is intended to be pin compatible with
standard serial EEPROM devices except for pins 1, 2 and
3, which are address pins in the standard part. Other
exceptions to the AT24C08 Serial EEPROM data sheet are
noted in the Serial EEPROM Exceptionssection later in
this document. Connection of an external coil antenna and
optional tuning capacitor, normally via a two conductor
wire, is all that is required to complete the RFID hardware
Throughout this document, the term readeris defined as
the base station that communicates with the chip. Under all
expected conditions, it actually serves as both a reader and
writer. The term tagis used to indicate the chip when
operating as an RFID transponder with the coil attached.
All bits are sent to or read from the device, most significant
bit first, in a manner consistent with the AT24C08 Serial
EEPROM. The bit fields in this document are
correspondingly listed with the MSB on the left and the LSB
on the right.
EEPROM Organization
The EEPROM memory is broken up into 8 blocks of 1K
bits (128 bytes) each. Within each block, the memory is
physically organized into 8 pages of 128 bits (16 bytes)
each. In some instances, accesses take place on a 32-bit
(4 byte) word basis. In addition to these 8K bits, there are
two more 128-bit pages that are used to store the access
protection and ID information. There are a total of 8448 bits
of EEPROM memory available on the AT24RF08C.
Access protection (both read and write) is organized on a
block basis for blocks 1 through 7 and on a page and block
basis for block 0. Protection information for these blocks
and pages is stored in one of the additional pages of
EEPROM memory that is addressed separately from the
main data storage array. See Access Protectionon page
3 for more details.
The ID value (see ID Configurationon page 7) is located
in the ID page of the EEPROM, the second of the additional
16 byte pages.
Writes from the serial port may include from one to 16
bytes at a time, depending on the protocol followed by the
bus master. Accesses to the EEPROM from the RFID port
are on either a word (32 bits) or page (128 bits) basis only.
All page accesses must be properly aligned to the internal
EEPROM page.
The EEPROM memory offers an endurance of 100,000
write cycles per byte, with 10 year data retention. Writes to
the EEPROM and tamper bit take less than 10 ms to
Completion time for writes initiated from the RFID port are
different depending on the situation. When external power
is supplied to the chip through the VCC pin, writes to the
EEPROM and tamper bit take less than 11.8 ms when
measured from the last modulation edge before the write to
the first after the write. When powered from the coil pins at
125 KHz, the EEPROM write time will be 5.8 ms and the
tamper write time will be 7.9 ms.
After manufacturing, all EEPROM bits except in the device
revision byte (see Access Protectionpage 5) will be set to
a value of 1 and the tamper bit will be set to 0.
Device Access
The third device address bit in the two wire protocol that is
usually matched to A2 (pin 3) on a standard AT24C08 serial
EEPROM is internally connected high, so device
addresses A8 through AF (hex) are used to access the
memory on the chip. The general command encoding used
by the serial port for EEPROM accesses is shown below in
Device Access Examples, where B2-0 is the block number,
P2-0 is the page number within the block and A3-0 is the byte
address within the page. Bits denoted as xare ignored by
the device.
The PROT pin is used as a power good signal. When this
pin is low, the serial port is held in reset and all sticky bits
are set to one. When high, activity on the serial bus is
Device Access Examples
For Write Operations:
1 0 1 0 1 B2 B1 0
B0 P2 P1 P0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
For Read Operations:
D7 D6 D5 D4 D3 D2 D1 D0
2 AT24RF08C

ATMEL Corporation 24RF08C
Access Protection
All access protection bits are stored on a separate page of
the EEPROM that is not accessed using the normal
commands of an AT24C08 memory. See the Access
Protection Pagesection on page 5, for more detail on this
The RFID Access (RF) fields in the Access Protection Page
determines whether or not the corresponding block within
the memory can be read or written via the RFID interface. If
an illegal command is attempted, the command will be
aborted. The MSB, if clear, prohibits all accesses from the
RFID port, and the LSB if clear prohibits writes from the
RFID port. The fields are stored in the EEPROM and
organized as follows:
RFID Access Fields (RF)
LSB Function
0 0 No accesses permitted from RFID port
0 1 No accesses permitted from RFID port
1 0 Reads only from the RFID port
1 1 No restrictions for RFID accesses
The Protection Bits (PB) fields in the Access Protection
Page determine what type of accesses will be permitted via
the serial port for each of the blocks on the chip. If an illegal
access is attempted, the command will be NACKed. The
MSB, if clear, prohibits all accesses to the block, and the
LSB if clear prohibits writes. The fields are stored in the
EEPROM and are organized as follows:
Protection Bits (PB)
LSB Function
0 0 No accesses permitted in the block
0 1 No accesses permitted in the block
1 0 Read only, writes cause a NACK
Read/write - No access constraints for
data within this block
The Tamper Write (TW) bits within the access protection
page control whether or not a write will be permitted into
the corresponding block of memory when the Tamper Bit is
set. If the Tamper Bit is a 1 and the TW bit is a 0, then
writes to that block from the RFID port are not permitted. In
all other cases, writes are permitted according to the RF
field value for that block. The value of this bit does not affect
accesses from the serial port.
Accessed within the Access Protection Page is an
individual CMOS Sticky Bit (SB) for each of the 8 blocks on
the device. When the value of the sticky bit is 0, the
Protection Bits (PB) for the corresponding block may not be
changed via the software. These bits are all set to one
when power is initially applied or when the PROT pin is low.
These sticky bits may be written only to a 0 via the serial
interface using the standard serial write operations.
Reading the sticky bits does not affect their state.
Because access permissions are set individually for each
of the blocks, all reads via the serial port will only read
bytes within the block that was specified when the current
address was latched into the device (with a write
command). The block address bits (B2 or B1) that are sent
with the write command are ignored on a read command.
After the read of the last byte within a block, the internal
serial address wraps around to point at the beginning of
that block. After the write of the last byte in a page, the
internal address is wrapped around to point to the
beginning of that page. If more than 16 bytes are sent to
the device with a write command, the data written to any
overlapping bytes will be corrupted.
If the WP pin is high, all write operations are prohibited
from the serial port, although write commands may be used
to set the address for a subsequent read command.
Block 0 Write Protection Bits
The AT24RF08C provides a mechanism to divide block 0
into eight 128-bit (16 byte) pages that can be individually
protected against writes from either port. These eight write
protection (WP) bits are stored within a byte of the access
protection page and are organized such that the LSB
protects the first 128 bits and so on. If a bit in this byte is set
to a one and the PB0 field is set to 11, then writes are
permitted on the page corresponding to the WP bit. If the
WP bit is set to a 0 or the PB0 is any value other than 11,
then writes are not permitted in that page.
The Write Protection hierarchy for serial accesses is shown
on the following page. In this drawing the bits within the
boxes to the left of the arrows are the only thing that
determine whether or not the bit in the box to the right of
the arrow can be written. Read access control is not shown
in this diagram. Addresses listed in this diagram are for the
serial port assuming that the R/W bit in the command byte
is set to 0.

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