Document
STP3NA100 STP3NA100FI
N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR
TYPE STP3NA100 STP3NA100FI
s s s s s s s
V DSS 1000 V 1000 V
R DS(on) <5 Ω <5Ω
ID 3.5 A 2A
TYPICAL RDS(on) = 4.3 Ω ± 30V GATE TO SOURCE VOLTAGE RATING 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED REDUCED THRESHOLD VOLTAGE SPREAD TO-220
3 1 2
1 2
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APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE
TO-220FI
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID IDM ( • ) P tot V ISO T stg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 o C Drain Current (pulsed) Total Dissipation at T c = 25 o C Derating Factor Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature
o
Value STP3NA100 STP3NA100FI 1000 1000 ± 30 3.5 2.0 14 110 0.88 -65 to 150 150 2.0 1.2 14 45 0.36 2000
Unit V V V A A A W W/ o C V
o o
C C 1/9
(•) Pulse width limited by safe operating area
February 1998
STP3NA100/FI
THERMAL DATA
TO-220 R thj-case R thj-amb R thc-sink Tl Thermal Resistance Junction-case Max 1.14 62.5 0.5 300 ISOWATT220 2.78
o o o
C/W C/W C/W o C
Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose
AVALANCHE CHARACTERISTICS
Symbol I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max, δ < 1%) Single Pulse Avalanche Energy (starting T j = 25 o C, I D = I AR , VDD = 50 V) Max Value 3.5 170 Unit A mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Conditions I D = 250 µ A VGS = 0 Min. 1000 25 250 ± 100 Typ. Max. Unit V µA µA nA
Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = ± 30 V
T c = 125 o C
ON (∗)
Symbol V GS(th) R DS(on) ID(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance V DS = VGS V GS = 10V Test Conditions ID = 250 µ A I D = 1.5 A 3.5 Min. 2.25 Typ. 3 4.3 Max. 3.75 5 Unit V Ω A
On State Drain Current V DS > I D(on) x R DS(on)max V GS = 10 V
DYNAMIC
Symbol g fs ( ∗ ) C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions V DS > I D(on) x R DS(on)max V DS = 25 V f = 1 MHz I D = 1.5 A V GS = 0 Min. 1.5 Typ. 3 1100 85 20 1430 110 30 Max. Unit S pF pF pF
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STP3NA100/FI
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions V DD = 500 V R G = 4.7 Ω V DD = 800 V I D = 1.7 A V GS = 10 V I D = 3.5 A V GS = 10 V Min. Typ. 20 27 48 8 23 Max. 27 35 65 Unit ns ns nC nC nC
SWITCHING OFF
Symbol t r(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions V DD = 800 V I D = 3.5 A R G = 47 Ω V GS = 10 V (see test circuit, figure 5) Min. Typ. 62 22 95 Max. 85 30 125 Unit ns ns ns
SOURCE DRAIN DIODE
Symbol I SD I SDM (• ) V SD ( ∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 3.5 A V GS = 0 1000 15 35 I SD = 3.5 A di/dt = 100 A/ µ s o V DD = 100 V T j = 150 C (see circuit, figure 5) Test Conditions Min. Typ. Max. 3.5 14 1.6 Unit A A V ns µC A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area
Safe Operating Area for TO-220
Safe Operating Area for TO-220FP
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STP3NA100/FI
Thermal Impedance for TO-220 Thermal Impedance forTO-220FP
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
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STP3NA100/FI
Gate Charge vs Gate-source Voltage Capacitance Variations
Normalized Gate Threshold Voltage vs Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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STP3NA100/FI
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STP3NA100/FI
TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0..