MT48LC16M16LF

PRELIMINARY‡ 256Mb: x16 MOBILE SDRAM MOBILE SDRAM Features Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes Self Refresh Mode 64ms, 8,192-cycle refresh LVTTL-compatible inputs and outputs Low voltage power supply Temperature Compensated Self Refresh (TCSR) Option Marking VDD/VDDQ LC 3.3V/3.3V G 3.0V/3.0V V 2.5V/2.5V-1.8V Configurations 16M16 16 Meg x 16 (4 Meg x 16 x 4 banks) Plastic Packages - OCPL TG 54-pin TSOP (400 mil)1 P 54-pin TSOP (400 mil) Lead-Free1 FG 54-ball VFBGA (8mm x 14mm)2 BG 54-ball VFBGA (8mm x 14mm) Lead-Free2 F8 54-ball VFBGA (11mm x 8mm)2 B8 54-ball VFBGA (11mm x 8mm) Lead-Free2 Timing (Cycle Time) -75 7.5ns @ CL = 3 (133MHz) -8 8.0ns @ CL = 3 (125 MHz) -10 9.6ns @ CL = 3 (104 MHz) Self Refresh None Standard Operating Temperature None Commercial (0oC to + 70oC) XT Extended (-25oC to + 75oC) IT Industrial (-40oC to + 85oC) NOTE: 1. Contact Factory for availability. 2. Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, www.micron.com/decoder. MT48LC16M16LF, MT48G16M16LF, MT48V16M16...