8 bit. BS62LV4006 Datasheet

BS62LV4006 bit. Datasheet pdf. Equivalent

Part BS62LV4006
Description Very Low Power/Voltage CMOS SRAM 512K X 8 bit
Feature ( DataSheet : www.DataSheet4U.com ) BSI „ FEATURES Very Low Power/Voltage CMOS SRAM 512K X 8 bit .
Manufacture Brilliance Semiconductor
Datasheet
Download BS62LV4006 Datasheet

( DataSheet : www.DataSheet4U.com ) BSI „ FEATURES Very Lo BS62LV4006 Datasheet
Recommendation Recommendation Datasheet BS62LV4006 Datasheet




BS62LV4006
( DataSheet : www.DataSheet4U.com )
BSI Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BS62LV4006
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Fully static operation
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4006TC
BS62LV4006STC
BS62LV4006SC
BS62LV4006EC
BS62LV4006PC
BS62LV4006TI
BS62LV4006STI
BS62LV4006SI
BS62LV4006EI
BS62LV4006PI
OPERATING
Vcc
TEMPERATURE RANGE
+0 O C to +70 O C 2.4V ~ 5.5V
-40 O C to +85O C 2.4V ~ 5.5V
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
„ DESCRIPTION
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4006 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
SPEED
( ns )
55ns :3.0~5.5V
70ns :2.7~5.5V
POWER DISSIPATION
STANDBY
( I CCSB1 , Max )
Operating
( I CC , Max )
Vcc = 3.0V
Vcc =5.0V
Vcc = 3.0V
70ns
Vcc =5.0V
70ns
55 / 70
5uA
30uA 24mA
58mA
55 / 70
10uA
60uA 25mA
60mA
PKG
TYPE
TSOP- 32
STSOP-32
SOP -32
TSOP2 - 32
PDIP -32
TSOP - 32
STSOP - 32
SOP - 32
TSOP2- 32
PDIP - 32
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 BS62LV4006SC 25
9
10
11
BS62LV4006SI
BS62LV4006EC
BS62LV4006EI
BS62LV4006PC
24
23
22
12 BS62LV4006PI 21
13 20
14 19
15 18
16 17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4006TC
BS62LV4006STC
BS62LV4006TI
BS62LV4006STI
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
Vdd
GND
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 2048
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
2048
8 Column I/O
Write Driver
Sense Amp
8
256
Column Decoder
16
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
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Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201w-BwSw6.2DLaVt4a0S0h6eet4U.com
1
Revision 1.1
Jan. 2004



BS62LV4006
BSI
„ PIN DESCRIPTIONS
Name
A0-A18 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
Vcc
GND
BS62LV4006
Function
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
„ TRUTH TABLE
MODE
WE CE OE
Not selected
X
H
X
Output Disabled
H
L
H
Read
HL L
Write
LLX
I/O OPERATION
High Z
High Z
DOUT
DIN
Vcc CURRENT
I , ICCSB CCSB1
ICC
ICC
ICC
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
TBIAS
TSTG
PT
IOUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
UNITS
V
OC
OC
W
mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
„ OPERATING RANGE
RANGE
Commercial
AMBIENT
TEMPERATURE
0 O C to +70 O C
Industrial
-40 O C to +85 O C
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
VIN=0V
VI/O=0V
MAX.
6
8
UNIT
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV4006
2
Revision 1.1
Jan. 2004





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