SR71040A

( DataSheet : www.DataSheet4U.com ) PRELIMINARY MIPS64 SUPERSCALAR MICROPROCESSOR TM SR71040A ENGINES FOR THE DIGITA T L AGE TM The SR71040A microprocessor is a MIPS64- TM compatible processor based on the proven 0.15u SR71010A design. The product provides a low cost, high-performance MIPS64-compatible processor to enable a new class of processor-based embedded systems, and also to provide an upgrade path for users of R4000and R5000-class processors in low- to mid-range embedded systems. The SR71040A microprocessor comprises the following features: · · · · · · 600 to 800MHz two-way superscalar 9 stage pipeline with out of order executions and hardware branch prediction. Primary instruction and data caches are both 16KB, and 2-way set associative On-chip secondary cache is 128KB and is 4-way set associative 133MHz SysAD bus interface IEEE 754 compatible floating point unit The SR71040A is available in two speed grades of 600MHz and 800MHz in a 256 pin TBGA package. iTLB PC gen i-cache decode register file dispatch BHT buffer FP reg file dispatch SysAD BRU ALUx ALUy LD/ST dTLB MOV TB LOAD MATH MACC Dcache L2 cache SR71040A Architecture Block Diagram High performance architecture · Fully MIPS64 Instruction Set Architecture (ISA) compliant True 2-way superscalar architecture · Dual fetch, dual dispatch, up to 6-issue, up to 6-execute, dual-commit · Maximum operation rate of pipeline: 2 instructions per cycle · Out-of-order issue and dispatch · In-order ret...