SR71010A

( DataSheet : www.DataSheet4U.com ) TM TM SR71010A MIPS64 SUPERSCALAR MICROPROCESSOR ENGINES FOR THE DIGITAL AGE The SR71010A is a true 2-way superscalar MIPS64 TM microprocessor with a 9-stage pipeline designed for high performance applications such as networking, image processing and internet servers. The highly efficient architecture can operate up to a maximum frequency of 600MHz, and includes dual instruction fetch, up to 6-issue, up to 6-execute, and dual-commit, to sustain an instruction throughput rate of 2 instructions per cycle. Instruction execution efficiency is maximized for the deep pipeline by including sophisticated branch prediction techniques, that keep the pipeline fully utilized. The SR71010A also maximizes system per formance and reduces system cost with integrated on-chip 512 KByte L2 cache, L3 cache controller and L3 cache tags. The SR71010A is a fully static design with dynamic power saving features that minimize power consumption. The high performance system interface, which is fully compatible to R4xxx/5xxx/7xxx SysAD interface, can operate up to 133MHz with split transactions and out- of- order return. The SR71010A includes a high - per formance floating point unit (FPU) that is fully MIPS64 compliant. The FPU is decoupled from the integer pipeline enabling autonomous integer and floating point operations. iTLB PC gen i-cache decode BHT buffer SysAD & L3 Interface register file dispatch FP reg file dispatch BRU ALUx ALUy LD/ST dTTB ...