S19235PB11

( DataSheet : www.DataSheet4U.com ) S19235 OC-192 SONET/SDH/FEC/GbE 16-bit Transceiver and the serial receive interface. The system timing circuitry consists of a highspeed phase detector, clock dividers, and clock distribution. The device utilizes on-chip clock synthesis PLL components that allow the use of a slower external clock reference, 155.52 MHz or 622.08 MHz (or equivalent FEC/10GbE rate), in support of existing system clocking schemes. The low-jitter, 16-bit, Low Voltage Differential Signaling (LVDS) interfaces guarantee compliance with the bit-error rate requirements of the Telecordia and ITU-T standards. AMCC Suggested Interface Devices VERRAZANO (S2509) Quad STS-48 SONET/SDH/ Digital Wrapper Backplane SERDES STS-192 POS/ATM SONET/ SDH Mapper STS-192 POS/ATM SONET/ SDH Mapper Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and FEC Device STS-192 Pointer Processor Product Brief PB1204_v2.01_10/03/03 – At a Glance – 35 92 S1 General Features Operational from 9.953 Gbps to 11.1 Gbps Low Power (1100 mW Typical) 1.2 V and 1.8/2.5/3.3 V Power Supply Built-In Self Test (BIST) Feature with error counter On-chip High-Frequency PLL for Clock Generation and Clock Recovery 16-bit LVDS Parallel Data Path TX and RX Lock Detect Indication Serial and Reference Loop Timing Modes Line and Diagnostic Loopback Mode for Faulty Node Identification Operational Temperature Range Up to 85°C Supports Management Data Bus for Control I/O Com...