Hardware Specifications. XPC855TZP80D4 Datasheet

XPC855TZP80D4 Specifications. Datasheet pdf. Equivalent

Part XPC855TZP80D4
Description (XPC860 Series) Family Hardware Specifications
Feature ( DataSheet : www.DataSheet4U.com ) Advance Information MPC860EC Rev. 6.3 9/2003 MPC860 Family Hard.
Manufacture Motorola
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XPC855TZP80D4
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Advance Information
MPC860EC
Rev. 6.3 9/2003
MPC860 Family
Hardware Specications
This hardware specification contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the MPC860 family.
This hardware specification covers the following topics:
Topic
Section 1, “Overview”
Section 2, “Features”
Section 3, “Maximum Tolerated Ratings”
Section 4, “Thermal Characteristics”
Section 5, “Power Dissipation”
Section 6, “DC Characteristics”
Section 7, “Thermal Calculation and Measurement”
Section 8, “Layout Practices”
Section 9, “Bus Signal Timing”
Section 10, “IEEE 1149.1 Electrical Specifications”
Section 11, “CPM Electrical Characteristics”
Section 12, “UTOPIA AC Electrical Specifications”
Section 13, “FEC Electrical Characteristics”
Section 14, “Mechanical Data and Ordering Information”
Section 15, “Document Revision History”
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XPC855TZP80D4
Overview
1 Overview
The MPC860 Quad Integrated Communications Controller (PowerQUICC™) is a versatile one-chip
integrated microprocessor and peripheral combination designed for a variety of controller applications. It
particularly excels in communications and networking systems. The PowerQUICC unit is referred to as the
MPC860 in this hardware specification.
The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated Communications Controller
(QUICC), referred to here as the QUICC, which implements the PowerPC architecture. The CPU on the
MPC860 is a 32-bit PowerPCTM core that incorporates memory management units (MMUs) and instruction
and data caches and that implements the PowerPC instruction set. The communications processor module
(CPM) from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I2C)
channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory,
including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up
to two sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC860 family.
Table 1. MPC860 Family Functionality
Cache (Kbytes)
Ethernet
Part
Instruction
Cache
Data Cache
10T
10/100
MPC860DE
4
4
Up to 2
MPC860DT
4 4 Up to 2 1
MPC860DP
16 8 Up to 2 1
MPC860EN
4
4
Up to 4
MPC860SR
4
4
Up to 4
MPC860T
4 4 Up to 4 1
MPC860P
16 8 Up to 4 1
MPC855T
4411
1 Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC Family User’s Manual (MPC860UM/D, Rev. 2)
2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1)
ATM
Yes
Yes
Yes
Yes
Yes
Yes
SCC Reference 1
21
21
21
41
41
41
41
12
2 Features
The following list summarizes the key MPC860 features:
• Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch without conditional execution.
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction
caches are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are
two-way, set-associative with 128 sets.
2
MPC860 Family Hardware Specications
MOTOROLA





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