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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50111-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (× 16) FLASH MEMORY & 2M (× 16) STATIC RAM
MB84VD2008-10/MB84VD2009-10
s FEATURES
• Power supply voltage of 2.7 to 3.6 V • High performance 100 ns maximum access time • Operating Temperature –20 to +85°C — FLASH MEMORY • Simultaneous operations Read-while Erase or Read-while-Program • Minimum 100,000 write/erase cycles • Sector erase architecture Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD2008: Top sector MB84VD2009: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to "MBM29DL800TA/BA" data sheet in detailed function — SRAM • Power dissipation Operating : 50 mA max. Standby : 50 µA max. • Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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MB84VD2008-10/MB84VD2009-10
s BLOCK DIAGRAM
VCCf A0 to A18 A0 to A18 8 M bit Flash Memory VSS
RY/BY
RESET CEf
DQ0 to DQ15 VCCs A0 to A16 VSS
LBs UBs WE OE CEs
2 M bit Static RAM
2
MB84VD2008-10/MB84VD2009-10
s PIN ASSIGNMENTS
(Top View) A
6 5 4 3 2 1 CEs A10 OE A11 A13 WE
B
VSS DQ5 DQ7 A8 A17 VCCs
C
DQ1 DQ2 DQ4 A5 UBs A16
D
A1 A0 DQ0 DQ8 CEf VSS
E
A2 A3 A6 DQ3 DQ10 DQ9
F
A4 A7 A18 DQ12 VCCf DQ11
G
N.C. RY/BY RESET A12 DQ6 DQ13
H
A9 A14 A15 LBs DQ15 DQ14
Table 1 Pin Configuration
Pin A0 to A16 A17 to A18 DQ0 to DQ15 CEf CEs OE WE RY/BY UBs LBs RESET N.C. VSS VCCf VCCs
Function Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM)
Input/ Output I I I/O I I I I O I I I — Power Power Power
3
MB84VD2008-10/MB84VD2009-10
s PRODUCT LINE UP
Flash Memory Ordering Part No. VCC = 3.0 V
+0.6 V –0.3 V
SRAM
MB84VD2008-10/MB84VD2009-10 100 100 40 85 85 45
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s BUS OPERATIONS
Table 2 User Bus Operations Opera.