Mobile FCRAM. MB84VD23381HJ Datasheet

MB84VD23381HJ FCRAM. Datasheet pdf. Equivalent

Part MB84VD23381HJ
Description 64M (X16) FLASH MEMORY & 16M (X16) Mobile FCRAM
Feature FUJITSU SEMICONDUCTOR DATA SHEET DS05-50312-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCR.
Manufacture Fujitsu Media Devices
Datasheet
Download MB84VD23381HJ Datasheet

FUJITSU SEMICONDUCTOR DATA SHEET DS05-50312-1E Stacked MCP MB84VD23381HJ Datasheet
FUJITSU SEMICONDUCTOR DATA SHEET DS05-50312-1E Stacked MCP MB84VD23381HJ-70 Datasheet
Recommendation Recommendation Datasheet MB84VD23381HJ Datasheet




MB84VD23381HJ
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50312-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64M (×16) FLASH MEMORY &
16M (×16) Mobile FCRAMTM
MB84VD23381HJ-70
s FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
70 ns maximum random access time (Flash)
60 ns maximum random access time (FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 56-ball BGA
s PRODUCT LINEUP
Flash
Supply Voltage (V)
Max Random Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
+0.1 V
VCCf* = 3.0 V –0.3 V
70
70
30
* : Both VCCf and VCCr must be the same level when either part is being accessed.
s PACKAGE
56-ball plastic FBGA
(Continued)
FCRAM
+0.1 V
VCCr* = 3.0 V –0.3 V
60
60
35
BGA-56P-M04



MB84VD23381HJ
MBVD23381HJ-70
(Continued)
— FLASH MEMORY
Simultaneous Read/Write operations (Dual Bank)
FlexBankTM*1
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
Two virtual Banks are chosen from the combination of four physical banks.
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
Minimum 100,000 program/erase cycles
Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
WP/ACC input pin
At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector
protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
Embedded EraseTM*2 Algorithms
Automatically preprograms and erases the chip or any sector
Embedded ProgramTM*2 Algorithms
Automatically writes and verifies data at specified address
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
Low VCCf write inhibit 2.5 V
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Please refer to “MBM29DL64DH“ Datasheet in deteiled function
(Continued)
2





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