LAN Transceivers. PE-68532G Datasheet

PE-68532G Transceivers. Datasheet pdf. Equivalent

Part PE-68532G
Description (PE-6853xG) Fastpulse High Speed LAN Transceivers
Feature ( DataSheet : www.DataSheet4U.com ) FASTPULSE HIGH SPEED LAN TRANSCEIVERS High performance transcei.
Manufacture Pulse Engineering
Datasheet
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PE-68532G
( DataSheet : www.DataSheet4U.com )
FASTPULSE HIGH SPEED
LAN TRANSCEIVERS
High performance transceivers for
ATM 155 Mbps, 100Base-TX, and
TP-FDDI
Integrated drop-in frontend solution
Footprint compatible with popular
LCF 9-pin Fiber Optic Transceivers
Part Number Chart
Part Number
PE-68531G
PE-68532G, PE-68538G
PE-68537G
Note: Also available without metallic case: use suffix “C”, eg. PE-68532C.
Application
TP-FDDI
ATM 155 Mbps
100Base-TX
Standard
ANSI X3T12, TP-PMD
ATM-UNI-PMD STS-3c
IEEE 802.3u PMD
General Description
The FASTPULSE high speed LAN transceivers provide high
performance, cost-effective solutions for ATM 155 Mbps, TP-
FDDI and Fast Ethernet 100Base-TX frontends. The transceivers
interface the standard “fiber” PECL interface to UTP-5 cable,
integrating the transceiver IC, magnetics and connector in the
process. The highly compact design implements the entire
Physical Media Dependent (PMD) circuit in the standard 9-pin
form factor, which reduces component count and board space.
This modular transceiver approach, minimizes the design effort
and risk of implementing 100 Mbps + frontends.
Employing FASTPULSE technology, these transceivers integrate
the full transmit/receive interface functions of signal encoding/
decoding, adaptive equalization, DC restoration, signal filtering,
and isolation. This integrated approach, coupled to the novel
circuit design, results in a high performance frontend which
eliminates many of the conventional design compromises and
parasitic elements which plague high speed designs. The long
design cycle of selecting and optimizing the sensitive analog
IC/magnetic frontend is essentially replaced with a single-shot,
single-device approach. The compact 9-pin footprint matches the
industry standard 9-pin LCF fiber optic transceivers (AMP, HP,
etc.), allowing a common board design to accommodate both
fiber and copper options. The transceiver also allows existing
fiber designs to be upgraded for UTP support with minimal
design effort.
The PE68531G is a TP-FDDI transceiver which adheres to the
ANSI TP-PMD standard and employs MLT3 signaling to
support 100 Mbps (125 Mbaud) over 100 m UTP-5 cable. The
PE68532/38G are ATM transceivers which adhere to ATM-UNI-
PMD standard and employ NRZ signaling to support 155 Mbps
over 100 m UTP-5 cable. The PE-68532G is configured for the
adapter node of a network and the PE-68538G for the switch or
hub node. The PE-68537G is a 100Base-TX transceiver which
adheres to IEEE802.3u standard and employs MLT3
signaling to support 100 Mbps (125 Mbaud) over 100 m of
UTP-5 (2-pair) cable.
Features
s UTP Transceivers for ATM 155 Mbps, TP-FDDI and
100Base-TX
s Drop in replacement for standard 9-pin fiber optic
transceivers
s Full compliance with PMD standards: ATM, ANSI and IEEE
s Supports 100 m of Unshielded Twisted Pair,
Category 5 cable
s Implements full adaptive equalization and baseline
wander correction
s Excellent transmit and receive jitter performance
s EMC optimized design provides for low emissions and
high immunity (ESD protection per IEC 801)
s Direct PECL logic interface to PHY layer chip sets
s Offers simple, low-cost upgrade from existing fiber designs
s Offers flexibility of single UTP/fiber board
s Compact footprint enables efficient single/multiport designs
s 1500 Vrms voltage isolation
s Wavesolder and aqueous wash compatible
s ISO 9001 quality
s Two package options: with metallic case “G” and without
case “C”
Applications
The following products for ATM 155, TP-FDDI or
100Base-TX:
s Network adapter cards (ISA, PCI, VME etc.)
s Hubs or concentrators
s Motherboards (PC, workstation, industrial)
s Bridges, routers, switches
s Switch uplink modules
s LAN analyzers/test equipment
s Point to point links (Telecom)
s Peripherals: storage, print servers, etwc.ww.DataSheet4U.com
U.S.A: TEL 619 674 8100 EUROPE: TEL 44 1483 401700 ASIA: TEL 65 287 8998 WEB: http://www.pulseeng.com
www.DataSheet4U.com
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H309.A (7/96)



PE-68532G
FASTPULSE HIGH SPEED
LAN TRANSCEIVERS
Block Diagram
GND 1
RD+ 2
RD- 3
BASELINE
RESTORATION
DECODER
(MLT3/NRZ) 1
AGC
AMPLIFIER
ADAPTIVE
EQUALIZER
FILTER &
TERMINATION
STAKE POST
SD+ 4
VCC 5
VCC 6
TD- 7
TD+ 8
SIGNAL
DETECT
ENCODER
(MLT3/NRZ) 1
TRANSMIT
AMPLIFIER
FILTER &
TERMINATION
T
E
R
M
I
N
A
T
I
O
N
GND 9
STAKE POST
Notes:
1. PE-68531/37G implement MLT3. PE-68532/38G implement NRZ
2. Dotted line indicates the transceiver IC function.
3. RJ-45 pinout shown is for PE-68531/32G. See pinout specifications for PE-68537/36G.
SHIELD
8
7
6
5
4
3
2
1
SHIELD
Functional Description
The key functions of the transceivers are outlined in the block
diagram above.
In the transmit channel, the PECL (100 K) signals from the PHY
chip set (TD±) are encoded to appropriate line coding and driven
out differentially by the edge-controlled transmit amplifier in the
transceiver IC. The wideband transformer provides the required
1500 V isolation and the common mode choke eliminates high
frequency common mode noise. The magnetics are tuned
specifically to the characteristics of the transceiver IC to give a
highly balanced system with optimum signal rise-time, minimum
jitter and low emissions. The transformers exhibit a high minimum
inductance in order to counter signal droop in the presence of DC
bias. The outputs are fully terminated with cable impedance (100
) to meet return loss specification. See electrical characteristics
section for full transmitter specifications.
In the receive channel, the incoming differential signal from the
cable passes through a wideband isolation transformer and the
choke, before being filtered and terminated for high frequency
noise rejection. The resulting differential signal is fed to
transceiver IC for adaptive equalization, baseline restoration and
line decoding. Adaptive equalization is necessary to compensate
for the frequency dependent attenuation and phase distortion
which the signal suffers in the cable. The optimum compensation
required will vary with cable length and so a high performance
adaptive equalizer is employed which constantly adjusts itself
by means of a data quantized feedback loop. The equalizer
characteristics reflect the EIA/TIA 568 cable standard and
extensive modeling of UTP-5 cable characteristics under real life
conditions. The operation of the equalizer can be seen in the
performance section. The baseline restoration loop performs a
DC restoration on the incoming signal (as defined in ANSI TP-
PMD recommendation) which may occur due to data pattern
dependent DC shifts and the inherent low frequency bandwidth
limitations of the channel and AC coupling transformers. If not
corrected, this DC drift (or baseline wander) can cause
degradation in signal/noise ratio and can result in data errors. The
baseline restoration loop in the transceiver constantly monitors
the incoming signal and restores the DC level to a nominal level.
The resulting amplified, equalized and DC restored signal is
decoded in the line decoder as per appropriate scheme and
driven out as differential 100 K PECL signals RD±. See electrical
characteristics section for full receiver specifications.
The signal detect function monitors the equalized incoming signal
to notify PHY controller that a valid signal is received. This is
explicitly required by the TP-FDDI specification and is optional for
ATM system designers. The SD signal is driven out as single-
ended PECL signal.
The unused signal pairs in the RJ-45 are terminated at their
common mode impedance to minimize EMI emissions.
U.S.A: TEL 619 674 8100 EUROPE: TEL 44 1483 401700 ASIA: TEL 65 287 8998 WEB: http://www.pulseeng.com
2 H309.A (7/96)





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