GVT7C1363A

( DataSheet : www.DataSheet4U.com ) 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for TA(GVTI)/A(CY) package version and two chip enables for B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions Address pipeline capability Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications JTAG boundary scan for B and T package version Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), , and ADV), Write Enables Burst Control Inputs (ADSC, ADSP (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). However, the CE2 chip enable ...