GVT7C1367A

( DataSheet : www.DataSheet4U.com ) CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Pipelined SRAM Features Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for performance (two cycle chip deselect, depth expansion without wait state) 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to V SS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for TA(GVTI)/A(CY) package version and two chip enables for B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions Address pipeline capability Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications JTAG boundary scan for B and T package version Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, an...