Flash Memory. HY27UF161G2M Datasheet

HY27UF161G2M Memory. Datasheet pdf. Equivalent

Part HY27UF161G2M
Description (HY27UF(08/16)1G2M / HY27SF(08/16)1G2M) 1Gbit (128Mx8bit/64Mx16bit) NAND Flash Memory
Feature ( DataSheet : www.DataSheet4U.com ) Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1.
Manufacture Hynix Semiconductor
Datasheet
Download HY27UF161G2M Datasheet

( DataSheet : www.DataSheet4U.com ) Preliminary HY27UF(08/1 HY27UF161G2M Datasheet
Recommendation Recommendation Datasheet HY27UF161G2M Datasheet




HY27UF161G2M
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
0.1
0.2
History
1) Initial Draft.
1) Correct Fig.10 Sequential out cycle after read
2) Add the text to Fig.1, Table.1, Table.2
- text : IO15 - IO8 (x16 only)
3) Delete ‘3.2 Page program NOTE 1.
- Note : if possible it is better to remove this constrain
4) Change the text ( page 10,13, 45)
- 2.2 Address Input : 28 Addresses -> 27 Addresses
- 3.7 Reset : Fig.29 -> Fig.30
- 5.1 Automatic page read after power up : Fig.30 -> Fig.29
5) Add 5.3 Addressing for program operation & Fig.34
1) Change TSOP, WSOP, FBGA package dimension & figures.
- Change TSOP, WSOP, FBGA package mechanical data
- Change FBGA thickness (1.2 -> 1.0 mm)
2) Correct TSOP, WSOP Pin configurations.
- 38th NC pin has been changed Lockpre(figure 3,4)
3) Edit figure 15,19 & table 4
4) Add Bad Block Management
5) Change Device Identifier 3rd Byte
- 3rd Byte ID is changed. (reserved -> don't care)
- 3rd Byte ID table is deleted.
1) Add Errata
tCLS tCLH tWP tALS tALH tDS tWC
Specification 0 10 25 0 10 20 50
Relaxed value 5 15 40 5 15 25 60
tR
25
27
0.3
2) LOCKPRE is changed to PRE.
- Texts, Table, Figures are changed.
3) Add Note.4 (table.14)
4) Block Lock Mechanism is deleted.
- Texts, Table, figures are deleted.
5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)
- Texts & Figures are added.
6) Edit the figures. (#10~25)
1) Change AC characteristics(tREH)
before: 20ns -> after: 30ns
0.4 2) Edit Note.1 (page. 21)
3) Edit the Application note 1,2
4) Edit The Address cycle map (x8, x16)
Draft Date Remark
Aug. 2004 Preliminary
Sep. 2004 Preliminary
Oct. 2004 Preliminary
Nov.29 2004 Preliminary
Jan.19 2005 Preliminary
Rev 1.1 / Nov. 2005
1



HY27UF161G2M
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Revision History
Revision
No.
0.5
History
1) Correct AC characteristics(tREH)
before: 30ns-> after: 20ns
2) Add Errata
Case
tRC
Specification Read(all)
50
Relaxed
value
Except for
ID Read
50
ID Read
60
tRP
20
20
25
1) Change AC characteristics
tDH
Before
10
0.6 After
15
2) Add tADL parameter
- tADL=100ns
3) Correct table.9
1) Correct AC Timing Characteristics Table
- Errata value is eddited.
- tADL(max) is changed to tADL(min).
2) Change Errata
- tREA is deleted from the errata
Case
tRC tRP
Before
Except for
ID Read
ID Read
50
60
20
25
0.7
After
Read (all) 60
25
3) Edit pin Description table
4) Delete Multiple Die & Stacked Devices Access
- Texts & tables are deleted.
5) Edit Data Protection texts
6) Add Read ID table
7) Add tOH parameter
- tOH=15ns(min.)
8) Add Marking Information
9) Correct application note.2
- tCS(2us) is changed to 100ns.
tREH
20
20
30
tREH
20
30
30
- Continued -
Draft Date Remark
tREA
30
30
30
Jan. 25. 2005 Preliminary
Mar. 09. 2005 Preliminary
Apr. 06. 2005 Preliminary
Rev 1.1 / Nov. 2005
2





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