D Flip-Flop. MC74AC273 Datasheet

MC74AC273 Flip-Flop. Datasheet pdf. Equivalent

Part MC74AC273
Description Octal D Flip-Flop
Feature MC74AC273, MC74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−.
Manufacture ON Semiconductor
Datasheet
Download MC74AC273 Datasheet

MC74AC273, MC74ACT273 Octal D Flip-Flop The MC74AC273/74ACT2 MC74AC273 Datasheet
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MC74AC273
MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip−Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
ACT273 Has TTL Compatible Inputs
These are Pb−Free Devices
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
(Top View)
Pinout: 20−Lead Packages Conductors
MODE SELECT-FUNCTION TABLE
Operating Mode
Reset (Clear)
Inputs
MR CP
LX
Dn
X
Load 1
HH
Load 0
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
L
H
L
www.onsemi.com
20
1
SOIC−20WB
SUFFIX DW
CASE 751D
20
1
TSSOP−20
SUFFIX DT
CASE 948E
PIN ASSIGNMENT
PIN
D0−D7
MR
CP
FUNCTION
Data Inputs
Master Reset
Clock Pulse Input
Q0−Q7
Data Outputs
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 8
1
Publication Order Number:
MC74AC273/D



MC74AC273
MC74AC273, MC74ACT273
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
MR
O0 O1 O2 O3 O4 O5 O6 O7
NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 1. Logic Diagram
www.onsemi.com
2





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