MC74AC273

Octal D Flip-Flop MC74AC273, MC74ACT273 The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW−to−HIGH clock transition, is transferred to the corresponding flip−flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Features Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip−Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version Outputs Source/Sink 24 mA ′ACT273 Has TTL Compatible Inputs These are Pb−Free Devices VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 20 19 18 17 16 15 14 13 12 11 DATA SHEET www.onsemi.com 1 SOIC−20W DW SUFFIX CASE 751D MARKING DIAGRAMS 20 XXXXXX AWLYYWWG 1 1 TSSOP−20 DT SUFFIX CASE 948E 20 XXXX XXXX ALYWG G 1 XXXXXX = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT PIN D0−D7 MR CP FUNCTION Data ...