4-INPUT MULTIPLEXER. MC74ACT253 Datasheet

MC74ACT253 MULTIPLEXER. Datasheet pdf. Equivalent

Part MC74ACT253
Description DUAL 4-INPUT MULTIPLEXER
Feature ( DataSheet : www.DataSheet4U.com ) MC74AC253 MC74ACT253 Dual 4ĆInput Multiplexer with 3ĆState Outp.
Manufacture Motorola
Datasheet
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MC74AC253, MC74ACT253 Dual 4-Input Multiplexer with 3-State MC74ACT253 Datasheet
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MC74ACT253
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MC74AC253
MC74ACT253
Dual 4ĆInput Multiplexer
with 3ĆState Outputs
The MC74AC253/74ACT253 is a dual 4-input multiplexer with 3-state outputs. It
can select two bits of data from four sources using common select inputs. The
outputs may be individually switched to a high impedance state with a HIGH on the
respective Output Enable (OE) inputs, allowing the outputs to interface directly with
bus oriented systems.
Multifunctional Capability
Noninverting 3-State Outputs
Outputs Source/Sink 24 mA
• ′ACT253 Has TTL Compatible Inputs
VCC OEb S0 I3b I2b I1b I0b Zb
16 15 14 13 12 11 10 9
12345678
OEa S1 I3a I2a I1a I0a Za GND
PIN NAMES
I0a–I3a
I0b–I3b
S0, S1
OEa
OEb
Za, Zb
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
3-State Outputs
DUAL 4-INPUT
MULTIPLEXER WITH
3-STATE OUTPUTS
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
TRUTH TABLE
Select
Inputs
Data Inputs
Output
Enable
S0 S1 I0 I1 I2 I3
XXXXXX
L L LXXX
L LHXXX
HLXLXX
H L XHXX
L HXX L X
LHXXHX
HHXXX L
HHXXXH
OE
H
L
L
L
L
L
L
L
L
Address inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Z
Z
L
H
L
H
L
H
L
H
LOGIC SYMBOL
OEa I0a I1a I2a I3a I0b I1b I2b I3b OEb
S0
S1
Za Zb
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FACT DATA
5-1
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MC74ACT253
MC74AC253 MC74ACT253
FUNCTIONAL DESCRIPTION
The MC74AC253/74ACT253 contains two identical
4-input multiplexers with 3-state outputs. They select two bits
from four sources selected by common Select inputs (S0, S1).
The 4-input multiplexers have individual Output Enable (OEa,
OEb) inputs which, when HIGH, force the outputs to a high
impedance (High Z) state. This device is the logic
implementation of a 2-pole, 4-position switch, where the
position of the switch is determined by the logic levels supplied
to the two select inputs. The logic equations for the outputs are
shown:
Za = OEa(I0aS1S0+I1aS1S0+
I2aS1S0+I3aS1S0)
Zb = OEb(I0bS1S0+I1bS1S0+
I2bS1S0+I3bS1S0)
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
OEb I3b
I2b I1b
LOGIC DIAGRAM
I0b S0 S1 I3a
I2a I1a
I0a OEa
Zb Za
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
FACT DATA
5-2





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