ADDRESSABLE LATCH. MC74ACT256 Datasheet

MC74ACT256 LATCH. Datasheet pdf. Equivalent

Part MC74ACT256
Description DUAL 4-BIT ADDRESSABLE LATCH
Feature ( DataSheet : www.DataSheet4U.com ) MC74AC256 MC74ACT256 Dual 4ĆBit Addressable Latch The MC74AC256.
Manufacture Motorola
Datasheet
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MC74ACT256
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MC74AC256
MC74ACT256
Dual 4ĆBit Addressable Latch
The MC74AC256/74ACT256 dual addressable latch has four distinct modes
of operation which are selectable by controlling the Clear and Enable inputs
(see Function Table). In the addressable latch mode, data at the Data (D) inputs
is written into the addressed latches. The addressed latches will follow the Data
input with all unaddressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous states and are
unaffected by the Data or Address inputs. To eliminate the possibility of entering
erroneous data in the latches, the enable should be held HIGH (inactive) while
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs
with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected
by the Address and Data inputs.
Combines Dual Demultiplexer and 8-Bit Latch
Serial-to-Parallel Capability
Output from Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Common Clear Input
Useful as Dual 1-of-4 Active HIGH Decoder
VCC MR E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
DUAL 4-BIT
ADDRESSABLE
LATCH
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
12345678
A0 A1 Da Q0a Q1a Q2a Q3a GND
LOGIC SYMBOL
Da Db
A0
E
A1 MR
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
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FACT DATA
5-1
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MC74ACT256
MC74AC256 MC74ACT256
MODE SELECT-FUNCTION TABLE
Operating
Mode
Master Reset
Inputs
MR E D A0 A1
L HXXX
Q0
L
Outputs
Q1 Q2
LL
Q3
L
L L d L L Q=d L L L
Demultiplex (Active HIGH L L d H L L Q = d L
L
Decoder when D = H)
L LdLH L
L Q=d L
L L d H H L L L Q=d
Store (Do Nothing)
H H X X X q0 q1 q2 q3
Addressable
Latch
H L d L L Q = d q1 q2 q3
H L d H L q0 Q = d q2
q3
H L d L H q0
q1 Q = d q3
H L d H H q0 q1 q2 Q = d
H = HIGH Voltage Level Steady State
L = LOW Voltage Level Steady State
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in
which it was addressed or cleared.
E Da A0
A1
LOGIC DIAGRAM
MR Db
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC VCC or GND Current per Output Pin
Storage Temperature
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
±50
±50
–65 to +150
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
FACT DATA
5-2





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