D FLIP-FLOP. MC74ACT273 Datasheet

MC74ACT273 FLIP-FLOP. Datasheet pdf. Equivalent

Part MC74ACT273
Description OCTAL D FLIP-FLOP
Feature ( DataSheet : www.DataSheet4U.com ) MC74AC273 MC74ACT273 Octal D FlipĆFlop The MC74AC273/74ACT273 h.
Manufacture Motorola
Datasheet
Download MC74ACT273 Datasheet

MC74AC273, MC74ACT273 Octal D Flip-Flop The MC74AC273/74ACT2 MC74ACT273 Datasheet
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MC74ACT273
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MC74AC273
MC74ACT273
Octal D FlipĆFlop
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-
flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW
voltage level on the MR input. The device is useful for applications where the true
output only is required and the Clock and Master Reset are common to all storage
elements.
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
• ′ACT273 Has TTL Compatible Inputs
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN NAMES
D0–D7
MR
CP
Q0–Q7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
OCTAL D FLIP-FLOP
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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FACT DATA
5-1
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MC74ACT273
MC74AC273 MC74ACT273
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
MR
O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
MODE SELECT-FUNCTION TABLE
Operating Mode
Inputs
MR CP Dn
Reset (Clear)
L XX
Load 1
HH
Load 0
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
L
H
L
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC VCC or GND Current per Output Pin
Storage Temperature
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
±50
±50
–65 to +150
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
FACT DATA
5-2





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