Network FCRAM. TC59LM913AMB Datasheet

TC59LM913AMB FCRAM. Datasheet pdf. Equivalent


Part TC59LM913AMB
Description (TC59LM905AMB / TC59LM913AMB) Network FCRAM
Feature ( DataSheet : www.DataSheet4U.com ) TC59LM913/05AMB-50,-55,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGR.
Manufacture Toshiba Semiconductor
Datasheet
Download TC59LM913AMB Datasheet


( DataSheet : www.DataSheet4U.com ) TC59LM913/05AMB-50,-55, TC59LM913AMB Datasheet
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TC59LM913AMB
( DataSheet : www.DataSheet4U.com )
TC59LM913/05AMB-50,-55,-60
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
8,388,608-WORDS × 4 BANKS × 16-BITS Network FCRAMTM
16,777,216-WORDS × 4 BANKS × 8-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913/05AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB is organized as 8,388,608-words × 4 banks × 16
bits, TC59LM905AMB is organized as 16,777,216-words × 4 banks × 8 bits. TC59LM913/05AMB feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM913/05AMB can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM913/05AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM913/05
-50 -55 -60
tCK Clock Cycle Time (min)
CL = 3
CL = 4
5.5 ns
5.0 ns
6.0 ns
5.5 ns
6.5 ns
6.0 ns
tRC Random Read/Write Cycle Time (min)
25.0 ns
27.5 ns
30.0 ns
tRAC Random Access Time (max)
22.0 ns
24.0 ns
26.0 ns
IDD1S Operating Current (single bank) (max)
TBD
TBD
TBD
lDD2P Power Down Current (max)
TBD
TBD
TBD
lDD6 Self-Refresh Current (max)
TBD
TBD
TBD
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Fast cycle and Short Latency
Distributed Auto-Refresh cycle in 7.8 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
Organization: TC59LM813AMB : 8,388,608 words × 4 banks × 16 bits
TC59LM805AMB : 16,777,216 words × 4 banks × 8 bits
Power Supply Voltage VDD: 2.5 V ± 0.15V
VDDQ: 2.5 V ± 0.15 V
2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
Package:
60Ball BGA, 1mm × 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
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2003-04-21 1/49



TC59LM913AMB
TC59LM905AMB
PIN NAMES
PIN
A0~A14
BA0, BA1
DQ0~DQ7
CS
FN
PD
CLK, CLK
DQS
VDD
VSS
VDDQ
VSSQ
VREF
NC
NAME
Address Input
Bank Address
Data Input/Output
Chip Select
Function Control
Power Down Control
Clock Input
Write/Read Data Strobe
Power (+2.5 V)
Ground
Power (+2.5 V)
(for I/O buffer)
Ground
(for I/O buffer)
Reference Voltage
Not Connected
TC59LM913/05AMB-50,-55,-60
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x8
12345
Index
6
A VSS DQ7
B NC VSSQ
C DQ6 VDDQ
D NC DQ5
E NC VSSQ
F DQ4 VDDQ
G NC VSSQ
H NC DQS
J VREF VSS
K CLK CLK
L A12 PD
M A11 A9
N A8 A7
P A5 A6
R VSS A4
DQ0 VDD
VDDQ NC
VSSQ DQ1
DQ2 NC
VDDQ NC
VSSQ DQ3
VDDQ NC
NC NC
VDD A14
FN A13
CS NC
BA1 BA0
A0 A10
A2 A1
A3 VDD
2003-04-21 2/49







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