TC59LM836DMB

( DataSheet : www.DataSheet4U.com ) TC59LM836DMB-30,-33,-40 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TM 2,097,152-WORDS × 4 BANKS × 36-BITS Network FCRAM DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DMB is Network FCRAMTM containing 301,989,888 memory cells. TC59LM836DMB is organized as 2,097,152-words × 4 banks × 36 bits. TC59LM836DMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM836DMB can operate fast core cycle compared with regular DDR SDRAM. TC59LM836DMB is suitable for Network and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. FEATURES PARAMETER CL = 4 tCK tRC tRAC Clock Cycle Time (min) Random Read/Write Cycle Time (min) Random Access Time (max) CL = 5 CL = 6 -30 4.0 ns 3.33 ns 3.0 ns 20.0 ns 20.0 ns 380 mA 80 mA 10 mA TC59LM836DMB -33 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns 360 mA 75 mA 10 mA -40 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns 340 mA 70 mA 10 mA IDD1S Operating Current (single bank) (max) lDD2P Power Down Current (max) lDD6 Self-Refresh Current (max) Fully Synchronous Operation Double Data Rate (DDR) Data input/output are synchronized with both edges of ...