P8M644YL

SDRAM MODULE Features: JEDEC - Standard 168-pin (gold), dual in-line memory module (DIMM). TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive edge of system clock. Internal pipelined operation; column address can be changed every clock cycle. Quad internal banks for hiding row access/precharge. 64ms 4096 cycle refresh. All inputs, outputs, clocks LVTTL compatible. P4M644YL, P8M648YL 4M, 8M x 64 DIMM PIN ASSIGNMENT (Front View) 168-PIN DIMM Options: 4 - 4Mx16 SDRAM TSOP 8 - 4Mx16 SDRAM TSOP Part Number: P4M644YL-XX P8M648YL-XX KEY DIMM MODULE TIMING PARAMETERS Module Component Clock CAS Latency Marking Marking Freq -66CL2 -10/-12 66MHZ 2 or 3 -100CL3A -8A 100MHZ 3 GENERAL DESCRIPTION The S4M644YL and S8M648YL are high performance dynamic random-access 32MB and 64MB modules respectively. These modules are organized in a x64 configuration, and utilize dual bank architecture with a synchronous interface. All signals are registered on the positive edge of the clock signals CK0 through CK3. Read and write accesses to the SDRAM are burst oriented; accesses start at a location and continue for a programmed number of locations in a sequence. Accesses begin with an ACTIVE command, which is followed by a READ or WRITE command. ABSOLUTE MAXIMUM RATINGS: Voltage on Vcc Supply relative to Vss...................-1 to +4.6V Operating Temperature TA (Ambient) .............25 ° to +70 °C Storage Temperature .......