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16C550 Dataheets PDF



Part Number 16C550
Manufacturers ETC
Logo ETC
Description TL16C550
Datasheet 16C550 Datasheet16C550 Datasheet (PDF)

TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 D Capable of Running With All Existing TL16C450 Software D Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s) D After Reset, All Registers Are Identical to the TL16C450 Register Set D In the FIFO Mode, Transmitter and Receiver Are Each B.

  16C550   16C550


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TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 D Capable of Running With All Existing TL16C450 Software D Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s) D After Reset, All Registers Are Identical to the TL16C450 Register Set D In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU D False-Start Bit Detection D Complete Status Reporting Capabilities D 3-State TTL Drive Capabilities for Bidirectional Data Bus and Control Bus D In the TL16C450 Mode, Holding and Shift www.DataSheet4U.com Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16 × Clock D Programmable Baud Rate Generator Allows D Line Break Generation and Detection D Internal Diagnostic Capabilities: – Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, Framing Error Simulation D Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream D Fully Prioritized Interrupt System Controls D Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled D Faster Plug-In Replacement for National Semiconductor NS16550A description The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode†), the TL16C550A can be placed in an alternate mode (FIFO) to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers. The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered. The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 × clock for driving the internal transmitter logic. Provisions are included to use this 16 × clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link. † The TL16C550A can also be reset to the TL16C450 mode under software control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 N PACKAGE (TOP VIEW) FN PACKAGE (TOP VIEW) D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN www.DataSheet4U.com SOUT CS0 CS1 CS2 BAUDOUT XIN XOUT WR1 WR2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1 D4 D3 D2 D1 D0 NC VCC RI DCD DSR CTS D5 D6 D7 RCLK SIN NC SOUT CS0 CS1 CS2 BAUDOUT 7 8 9 10 11 12 13 14 15 16 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 17 29 18 19 20 21 22 23 24 25 26 27 28 MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY A0 A1 AS NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XIN XOUT WR1 WR2 VSS NC RD1 RD2 DDIS TXRDY ADS TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 block diagram S e l e c t Receiver Buffer Register Internal Data Bus Receiver FIFO 8 –1 D7 – D0 Line Control Register Receiver Buffer Register 10 SIN www.Data.


M511664C 16C550 MSM511664C


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