8 SRAM. MSM832TMB Datasheet

MSM832TMB SRAM. Datasheet pdf. Equivalent


HMP MSM832TMB
( DataSheet : www.DataSheet4U.com )
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
MSM832 - 020/025/35
ISSUE 4.3 : November 1998
32K x 8 SRAM
MSM832 - 020/025/35
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Issue 5.0 : April 2001
Description
The MSM832 is a high speed Static RAM organ-
ised as 32K x 8 available with access times of 20
25 or 35 ns. It features completely static opera-
tion with a low power standby mode and is 3.0V
battery back-up compatible. It is directly TTL
compatible and has common data inputs and
outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS High Speed Static RAM
Features
• Fast Access Times of 20/25/35 ns.
• JEDEC Standard footprint.
• Operating Power 1 W (max)
• Low Power Standby 13 mW (max) -L version.
• Low Voltage Data Retention.
• Directly TTL compatible.
• Completely Static Operation.
Block Diagram
A3
A4 X
A5 Address
A6
A7
Buffer
A8
A12
A13
A14
Row
Decoder
Memory Array
512 X 512
D0 I/O Column I/O
D7
Buffer
Column Decoder
WE Y Address Buffer
OE
CS
Pin Definitions
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
D0 11
D1 12
D2 13
GND 14
V,T
PACKAGE
TOPVIEW
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CS
19 D7
18 D6
17 D5
16 D4
15 D3
Package Details
Pin Count Description
Package Type
28
0.1" Vertical-in-LIne (VILTM)
V
28 0.3" Dual-in-line (SKINNY DIP) T
28 0.6" Dual-in-line
S
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1
Pin Functions
A0-A14
D0-7
CS
OE
WE
VCC
GND
Address inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
Power(+5V)
Ground
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MSM832TMB Datasheet
Recommendation MSM832TMB Datasheet
Part MSM832TMB
Description 32K x 8 SRAM
Feature MSM832TMB; ( DataSheet : www.DataSheet4U.com ) TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES MSM832 - 020/025/.
Manufacture HMP
Datasheet
Download MSM832TMB Datasheet




HMP MSM832TMB
ISSUE 4.3 : November 1998
MSM832 - 020/025/35
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to V (2)
SS
V -0.5V to +7 V
T
Power Dissipation
P 1W
T
Storage Temperature
TSTG -65 to +150 oC
Notes : (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol min
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
VCC
VIH
VIL
TA
TAL
TAM
4.5
2.2
-0.5
0
-40
-55
typ max Unit
5.0 5.5 V
- VCC+0.5 V
- 0.8 V
- 70 oC
- 85 oC ( Suffix I )
- 125 oC ( Suffix M, MB )
DC Electrical Characteristics (V = 5.0V±10%, T =-55°C to +125°C)
CC A
Parameter
Symbol Test Condition
min
Input Leakage Current
I
LI
VIN=0V to VCC
Output Leakage Current
I
LO
CS=VIH or OE=VIH ,VI/O= VSS to VCC ,WE=VIL
Average Supply Current
ICC CS=VIL,II/O=0mA, Min. Cycle, Duty=100%
Standby Supply Current
I
SB1
CS=VIH ,Min Cycle.
-L Version I
SB2
CSVCC-0.2V, 0.2VVINVCC-0.2V
Output Voltage
VOL IOL= 8.0 mA
V
OH
IOH= -4.0 mA
-2
-2
-
-
-
-
2.4
typ max Unit
- 2 µA
- 2 µA
- 182
mA
- 44 mA
- 2.3 mA
- 0.4 V
- -V
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol Test Condition
Input Capacitance
I/O Capacitance
CIN VIN = 0V
CI/O VI/O= 0V
Note: This parameter is not 100% tested.
min typ max Unit
- - 7 pF
- - 8 pF
2



HMP MSM832TMB
MSM832 - 020/025/35
ISSUE 4.3 : November 1998
Operating Modes
The table below shows the logic inputs required to control the MSM832 SRAM.
Mode
Not Selected
OutputDisable
Read
Write
CS OE WE VCCCurrent
1 XX
011
001
0 X0
ISB1,ISB2
ICC
ICC
ICC
1=V ,
IH
0=V ,
IL
I/O Pin Reference Cycle
High Z
High Z
DOUT
DIN
Power Down
Read Cycle
Write Cycle
X = Don't Care
Low V Data Retention Characteristics - L Version Only ( T =-55°C to +125°C)
cc A
Parameter
Symbol Test Condition
min
VCC for Data Retention
Data Retention Current -L Version
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes (1) t = Read Cycle Time
RC
VDR
ICCDR2
tCDR
tR
CSVCC-0.2V, VIN0V
2.0
VCC=2.0V, CSVCC-0.2V, VIN0V -
See Retention Waveform
0
See Retention Waveform
t (1)
RC
typ
-
-
-
-
max Unit
5.5 V
350 µA
- ns
- ns
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* Vcc=5V±10%
Output Load
I/O Pin
166
1.76V
30pF
3





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