Delay Chip. MC10EP195 Datasheet

MC10EP195 Chip. Datasheet pdf. Equivalent


ON Semiconductor MC10EP195
MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
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multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
MARKING
10 ps and a net range of up to 10.2 ns. The required delay is selected by
DIAGRAM*
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
LQFP−32
FA SUFFIX
CASE 873A
MCXXX
EP195
AWLYYWWG
32
1
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
1
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
1 32
QFN32
MN SUFFIX
CASE 488AM
MCXXX
EP195
AWLYYWWG
G
Select input pins D[10:0] may be threshold controlled by
XXX = 10 or 100
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to VCF and leave open VEF pin. The 1.5 V reference
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
between VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Maximum Input Clock Frequency >1.2 GHz Typical
Open Input Default State
Programmable Range: 0 ns to 10 ns
Safety Clamp on Inputs
Delay Range: 2.2 ns to 12.2 ns
A Logic High on the EN Pin Will Force Q to Logic
10 ps Increments
PECL Mode Operating Range:
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.6 V
Inputs
VBB Output Reference Voltage
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 19
1
Publication Order Number:
MC10EP195/D


MC10EP195 Datasheet
Recommendation MC10EP195 Datasheet
Part MC10EP195
Description 3.3V ECL Programmable Delay Chip
Feature MC10EP195; MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay C.
Manufacture ON Semiconductor
Datasheet
Download MC10EP195 Datasheet




ON Semiconductor MC10EP195
MC10EP195, MC100EP195
32 31 30 29 28 27 26 25
D8 1
24
D9 2
23
D10 3
22
IN 4
IN 5
MC10EP195
MC100EP195
21
20
VBB 6
19
VEF 7
18
VCF 8
17
9 10 11 12 13 14 15 16
VEE
D0
VCC
Q
Q
VCC
VCC
NC
Figure 1. 32−Lead LQFP Pinout (Top View)
D8 1
D9 2
D10 3
IN 4
IN 5
VBB 6
VEF 7
VCF 8
32 31
9 10
30 29 28 27
11 12 13 14
26 25
24 VEE
23 D0
22 VCC
21 Q
20 Q
19 VCC
18 VCC
17 NC
15 16
Exposed Pad (EP)
Figure 2. 32−Lead QFN (Top View)
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ON Semiconductor MC10EP195
MC10EP195, MC100EP195
Table 1. PIN DESCRIPTION
Pin Name
I/O Default State
Description
23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, Low Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
29, 30, 31, 32,
ECL Input
(Note 1)
1, 2
3
4
5
6
7
8
9, 24, 28
D[10]
IN
IN
LVCMOS, LVTTL,
ECL Input
ECL Input
ECL Input
VBB
VEF
VCF
VEE
Low
Low
High
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to VEE. (Note 1)
Noninverted Differential Input. Internal 75 kW to VEE.
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22
VCC
− Positive Supply Voltage. All VCC Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
10 LEN ECL Input
11
SETMIN
ECL Input
12
SETMAX
ECL Input
14 CASCADE ECL Output
15 CASCADE ECL Output
16 EN ECL Input
17 NC
Low Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.
Low Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
Low Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
− Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to VTT = VCC − 2 V.
− Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to VTT = VCC − 2 V.
Low Single−ended Output Enable Pin. Internal 75 kW to VEE.
− No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21
Q ECL Output
− Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
20
Q ECL Output
− Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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