IS61LF25636

( DataSheet : www.DataSheet4U.com ) IS61LF25632T/D/J IS61LF25636T/D/J IS61LF51218T/D/J 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs and data outputs JEDEC 100-Pin TQFP and 119-pin PBGA package Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0) Snooze MODE for reduced-power standby T version (three chip selects) J version (PBGA Package with JTAG) D version (two chip selects) JTAG Boundary Scan for PBGA. ISSI OCTOBER 2002 ® DESCRIPTION The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance and memories for commucation and networking applications. The IS61LF25632 is organized as 262,144 words by 32 bits and the IS61LF25636 is organized as 262,144 words by 36 bits. The IS61LF51218 is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers that are controlled by a positive-edgetriggered single clock input. Write cycles are internally...