Clock Source. ICS650R-01 Datasheet

ICS650R-01 Source. Datasheet pdf. Equivalent


Integrated Circuit Systems ICS650R-01
( DataSheet : www.DataSheet4U.com )
Description
The ICS650-01 is a low cost, low jitter, high
performance clock synthesizer for system
peripheral applications. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The
device provides clocks for PCI, SCSI, Fast
Ethernet, Ethernet, USB, and AC97. The user can
select one of three USB frequencies, and also one
of three AC97 audio frequencies. The OE pin puts
all outputs into a high impedance state for board
level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI
and Ethernet clocking.
The ICS650 can be mask customized to produce
any frequencies from 1 to 150 MHz.
ICS650-01
System Peripheral Clock Source
Features
• Packaged in 20 pin tiny SSOP (QSOP)
• Operating VDD of 3.3V or 5V
• Less than one ppm synthesis error in all clocks
• Inexpensive 14.31818 MHz crystal or clock input
• Provides Ethernet and Fast Ethernet clocks
• Provides SCSI clocks
• Provides PCI clocks
• Selectable AC97 audio clock
• Selectable USB clock
• OE pin tri-states the outputs for testing
• Selectable frequencies on three clocks
• Duty cycle of 40/60
• Advanced, low power CMOS process
Block Diagram
PSEL1:0
ASEL
USEL
14.31818 MHz
crystal X1/ICLK
or clock
X2
2
Crystal
Oscillator
Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffers
Output
Buffers
Output
Buffer
4
Processor Clocks
(Fast Ethernet,
SCSI, PCI )
Audio Clock
USB Clock
20 MHz
14.31818 MHz
Output Enable (all outputs)
MDS 650-01 C
1
Revision 092799
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
www.DataSheet4U.com


ICS650R-01 Datasheet
Recommendation ICS650R-01 Datasheet
Part ICS650R-01
Description System Peripheral Clock Source
Feature ICS650R-01; ( DataSheet : www.DataSheet4U.com ) ICS650-01 System Peripheral Clock Source Description The ICS650.
Manufacture Integrated Circuit Systems
Datasheet
Download ICS650R-01 Datasheet




Integrated Circuit Systems ICS650R-01
Pin Assignment
USEL 1
20 PSEL1
X2 2
19 PSEL0
X1/ICLK 3
18 PCLK2
VDD 4
17 PCLK3
VDD 5
16 VDD
GND 6
UCLK 7
15 ASEL
14 GND
20M 8
13 14.318M
ACLK 9
12 PCLK1
PCLK4 10
11 OE
20 pin (150 mil) SSOP
ICS650-01
System Peripheral Clock Source
Processor Clock (MHz)
PSEL1
0
0
0
M
M
M
1
1
1
PSEL0
0
M
1
0
M
1
0
M
PCLK1
25.00
TEST
TEST
40.00
33.3334
20.00
20.00
20.00
PCLK2,3
50.00
TEST
TEST
80.00
66.6667
40.00
33.3334
66.6667
PCLK4
18.75
TEST
TEST
20.00
25.00
25.00
25.00
25.00
1 Stops low all clocks except 20M
Audio Clock (MHz) USB Clock (MHz)
ASEL
0
M
1
ACLK
49.152
24.576
12.288
USEL
0
M
1
UCLK
12
24
48
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
USEL
X2
X1/ICLK
VDD
VDD
GND
UCLK
20M
ACLK
PCLK4
OE
PCLK1
14.318M
GND
ASEL
VDD
PCLK3
PCLK2
PSEL0
PSEL1
Type
I
XO
XI
P
P
P
O
O
O
O
I
O
O
P
I
P
O
O
I
I
Description
UCLK Select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to VDD. Must be same value as other VDD.
Connect to ground.
USB clock output per table above.
Fixed 20 MHz output for Ethernet. Only clock that runs when PSEL1=PSEL0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz buffered reference clock output.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
MDS 650-01 C
2
Revision 092799
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax



Integrated Circuit Systems ICS650R-01
ICS650-01
System Peripheral Clock Source
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Operating Voltage, VDD
3.0
Input High Voltage, VIH
Select inputs, OE
2
Input Low Voltage, VIL
Select inputs, OE
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA 2.4
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA
VDD-0.4
Operating Supply Current, IDD, at 5V
No Load, note 2
Operating Supply Current, IDD, at 3.3V
No Load, note 2
Short Circuit Current, VDD = 3.3
Each output
Input Capacitance
Except X1
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
All clocks
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle
At VDD/2
40
One Sigma Jitter, except ACLK
One Sigma Jitter, ACLK
Absolute Clock Period Jitter PCLK, UCLK, 20M
- 500
Typical
50
30
±50
7
14.31818
50
75
170
Maximum Units
7
VDD+0.5
70
260
150
V
V
C
C
C
5.5 V
V
0.8 V
V
0.4 V
V
mA
mA
mA
pF
MHz
1 ppm
1.5 ns
1.5 ns
60 %
ps
ps
500 ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33may be used for each clock output. The
14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a
fundamental mode, parallel resonant, 30ppm or better (to meet the Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by
the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
MDS 650-01 C
3
Revision 092799
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax







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