Clock Synthesizer. ICS650-05 Datasheet

ICS650-05 Synthesizer. Datasheet pdf. Equivalent


Integrated Circuit Systems ICS650-05
( DataSheet : www.DataSheet4U.com )
PRELIMINARY INFORMATION
ICS650-05
HDTV Clock Synthesizer
Description
The ICS650-05 is a low cost, low jitter, high
performance clock synthesizer designed to
produce 74.175824 MHz and 74.250000 MHz as
necessary for HDTV applications. Using our
patented analog Phase-Locked Loop (PLL)
techniques, the device uses a 27.0 MHz clock or
fundamental crystal input to produce buffered,
fixed clocks and a selectable frame rate clock for
HDTV systems.
Features
• Packaged in 20 pin tiny SSOP (QSOP)
• Input Frequency of 27.0 MHz
• Zero ppm synthesis error in output clocks
• Provides fixed 13.5 MHz, dual 27.0 MHz, and
54.0 MHz output clocks with a selectable Frame
Rate Clock of 74.175824 MHz or
74.250000 MHz
• Ideal for HDTV applications
• 3.3 V or 5.0 V operating voltage
Block Diagram
FRS
27.0 MHz
Clock
Synthesis
and
Control
Circuit
Input
Buffer/Crystal
Oscillator
Output
Buffer
Output
Buffer
Output
Buffers
Output
Buffers
Output
Buffer
FRCLK
54.0 MHz
13.5 MHz
27.0 MHz
27.0 MHz
OE (all outputs)
MDS 650-05 A
1
Revision 081199
Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
www.DataSheet4U.com


ICS650-05 Datasheet
Recommendation ICS650-05 Datasheet
Part ICS650-05
Description HDTV Clock Synthesizer
Feature ICS650-05; ( DataSheet : www.DataSheet4U.com ) PRELIMINARY INFORMATION ICS650-05 HDTV Clock Synthesizer Desc.
Manufacture Integrated Circuit Systems
Datasheet
Download ICS650-05 Datasheet




Integrated Circuit Systems ICS650-05
PRELIMINARY INFORMATION
ICS650-05
HDTV Clock Synthesizer
Pin Assignment
VDD 1
20 VDD
X2 2
19 OE
X1/ICLK 3
18 FRS
VDD 4
17 FRCLK
VDD 5
16 VDD
GND 6
15 GND
NC 7
14 GND
27M 8
13 54M
13.5M 9
12 27M
GND 10
11 GND
20 pin SSOP (QSOP)
FRCLK Output Select Table (in MHz)
FRS Pin 18
0
1
FRCLK Pin 17
74.175824
74.250000
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
VDD
X2
X1/ICLK
VDD
VDD
GND
NC
27M
13.5M
GND
GND
27M
54M
GND
GND
VDD
FRCLK
FRS
OE
VDD
Type
P
XO
XI
P
P
P
-
O
O
P
P
O
O
P
P
P
O
I
I
P
Description
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Connect to ground.
No Connect. Do not connect anything to this pin.
27 MHz buffered oscillator clock output.
13.5 MHz clock output.
Connect to ground.
Connect to ground.
27 MHz buffered clock output.
54 MHz buffered clock output.
Connect to ground.
Connect to ground.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Frame Rate Clock as shown on table.
Frame Rate Frequency Select input pin. Determines FRCLK output as shown on table.
Output Enable. Tri-states all clocks when low.
Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal
connections
MDS 650-05 A
2
Revision 081199
Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax



Integrated Circuit Systems ICS650-05
PRELIMINARY INFORMATION
ICS650-05
HDTV Clock Synthesizer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Operating Voltage, VDD
3.0
Input High Voltage, VIH
FRS, OE
2
Input Low Voltage, VIL
FRS, OE
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA 2.4
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA
VDD-0.4
Operating Supply Current, IDD, at 5V
No Load
Operating Supply Current, IDD, at 3.3V
No Load
Short Circuit Current, VDD = 3.3 V
Each output
Input Capacitance
Except X1
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
All clocks
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle
At VDD/2
40
One Sigma Jitter, ACLK
VDD= 3.3 V
VDD= 5.0 V
Absolute Clock Period Jitter
VDD= 3.3 V
VDD= 5.0 V
Typical
26
14
±50
7
27
50
100
40
±300
±200
Maximum Units
7
VDD+0.5
70
260
150
V
V
°C
°C
°C
5.5 V
V
0.8 V
V
0.4 V
V
mA
mA
mA
pF
MHz
1 ppm
1.5 ns
1.5 ns
60 %
ps
ps
ps
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
MDS 650-05 A
3
Revision 081199
Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax







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