ICS650R-05

( DataSheet : www.DataSheet4U.com ) PRELIMINARY INFORMATION ICS650-05 HDTV Clock Synthesizer Description The ICS650-05 is a low cost, low jitter, high performance clock synthesizer designed to produce 74.175824 MHz and 74.250000 MHz as necessary for HDTV applications. Using our patented analog Phase-Locked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal input to produce buffered, fixed clocks and a selectable frame rate clock for HDTV systems. Features Packaged in 20 pin tiny SSOP (QSOP) Input Frequency of 27.0 MHz Zero ppm synthesis error in output clocks Provides fixed 13.5 MHz, dual 27.0 MHz, and 54.0 MHz output clocks with a selectable Frame Rate Clock of 74.175824 MHz or 74.250000 MHz Ideal for HDTV applications 3.3 V or 5.0 V operating voltage Block Diagram Output Buffer Clock Synthesis and Control Circuit Output Buffer Output Buffers Output Buffers Output Buffer FRCLK 54.0 MHz 13.5 MHz FRS 27.0 MHz Input Buffer/Crystal Oscillator 27.0 MHz 27.0 MHz OE (all outputs) 1 Revision 081199 Printed 12/4/00 Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax MDS 650-05 A www.DataSheet4U.com PRELIMINARY INFORMATION ICS650-05 HDTV Clock Synthesizer Pin Assignment VDD X2 X1/ICLK VDD VDD GND NC 27M 13.5M GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD OE FRS FRCLK VDD GND GND 54M 27M GND FRCLK Output Select Table (in MHz) FRS Pin 18 0 1 FRCLK Pin 17 74.175824 7...