Clock Synthesizer. ICS650-12 Datasheet

ICS650-12 Synthesizer. Datasheet pdf. Equivalent


Integrated Circuit Systems ICS650-12
( DataSheet : www.DataSheet4U.com )
ICS650-12
MPEG Clock Synthesizer
Description
The ICS650-12 is a low cost, low jitter, high
performance clock synthesizer designed to
produce fixed clock outputs of 13.5 MHz and
27.0 MHz and four selectable clock outputs of two
Processor Clocks (PCLK1 and PCLK2), Audio
Clock (ACLK), and Communications Clock
(CCLK). Using our patented analog Phase-
Locked Loop (PLL) techniques, the device uses a
27.0 MHz clock or fundamental crystal input to
produce clocks ideal for Digital Video/MPEG-
based applications.
Features
• Packaged in 20 pin tiny SSOP (QSOP)
• Input Frequency of 27.0 MHz
• Zero ppm synthesis error in output clocks
• Provides fixed 13.5 MHz and 27.0 MHz.
Also provides two selectable Processor Clocks,
one Audio Clock, and one Communications Clock
• Ideal for Digital Video/MPEG-based applications
• 3.3 V or 5.0 V operating voltage
• Entire chip powers down (when CS1=CS0=0)
Block Diagram
PS2:0
AS2:0
CS1:0
27.0 MHz
crystal or
clock
Input
Buffer/Crystal
Oscillator
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
÷2
Output
Buffer
PCLK1
PCLK2
ACLK
CCLK
13.5 MHz
27.0 MHz
MDS 650-12 A
1
Revision 113000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
www.DataSheet4U.com


ICS650-12 Datasheet
Recommendation ICS650-12 Datasheet
Part ICS650-12
Description MPEG Clock Synthesizer
Feature ICS650-12; ( DataSheet : www.DataSheet4U.com ) ICS650-12 MPEG Clock Synthesizer Description The ICS650-12 is a.
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Datasheet
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Integrated Circuit Systems ICS650-12
ICS650-12
MPEG Clock Synthesizer
Pin Assignment
PS2 1
20 PS1
X2 2
19 PS0
X1 3
18 CCLK
VDD 4
17 PCLK2
CS1 5
16 VDD
GND 6
15 AS1
ACLK 7
14 GND
PCLK1 8
13 13.5M
CS0 9
12 27M
AS2 10
11 AS0
20 pin SSOP (QSOP)
PCLK1 and PCLK2 Select Table (in MHz)
PS2 PS1 PS0 PCLK1 PCLK2
0 0 0 108.00 54.00
0 0 1 55.00
27.5
0 1 0 66.67
33.33
0 1 1 80.00
40.00
1 0 0 54.00
27.00
1 0 1 81.00
40.5
1 1 0 50.00
25.00
1 1 1 60.00
30.00
ACLK Select Table (in MHz)
AS2 AS1 AS0 ACLK
0 0 0 12.288
0 0 1 11.2896
0 1 0 8.192
0 1 1 24.576
1 0 0 8.192
1 0 1 16.9344
1 1 0 18.432
1 1 1 11.2896
CCLK Select Table (in MHz)
CS1 CS0 CCLK
0 0 All off*
01
20.00
1 0 66.6666
11
24.576
*Note: Entire chip powers
down (outputs stop low)
when CS1 = CS0 = 0.
Pin Descriptions
Pin #
1
2
3
4, 16
5
6, 14
7
8
9
10
11
12
13
15
17
18
19
20
Name
PS2
X2
X1
VDD
CS1
GND
ACLK
PCLK1
CS0
AS2
AS0
27M
13.5M
AS1
PCLK2
CCLK
PS0
PS1
Type
I
XO
XI
P
I
P
O
O
I
I
I
O
O
I
O
O
I
I
Description
Processor Clock Select Pin 2. See above table.
Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.
Connect to +3.3 V or +5.0 V.
Communications Clock Select Pin 1. See above table.
Connect to ground.
Audio Clock Output. See above table.
Processor Clock Output 1. See above table.
Communications Clock Select 0. See above table.
Audio Clock Select Pin 2. See above table.
Audio Clock Select Pin 0. See above table.
27 MHz buffered clock output.
13.5 MHz clock output.
Audio Clock Select Pin 1. See above table.
Processor Clock Output 2. See above table.
Communications Clock Output. See above table.
Processor Clock Select Pin 0. See above table.
Prcoessor Clock Select Pin 1. See above table.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal
connections
MDS 650-12 A
2
Revision 113000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com



Integrated Circuit Systems ICS650-12
ICS650-12
MPEG Clock Synthesizer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
Soldering Temperature
Max of 10 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
-0.5
0
-65
7
VDD+0.5
70
260
150
V
V
°C
°C
°C
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA
Operating Supply Current, IDD, at 5V
No Load
Operating Supply Current, IDD, at 3.3V
No Load
Short Circuit Current, VDD = 3.3 V
Each output
Input Capacitance
Except X1
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
3.0
2
2.4
VDD-0.4
39
22
±50
7
5.5 V
V
0.8 V
V
0.4 V
V
mA
mA
mA
pF
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
One Sigma Jitter, ACLK
Absolute Clock Period Jitter
All clocks
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
VDD=3.3 V
VDD=5.0 V
VDD=3.3 V, Except CCLK=20 MHz
VDD=5.0 V, Except CCLK=20 MHz
40
27
0
50
100
40
±300
±200
MHz
1 ppm
1.5 ns
1.5 ns
60 %
ps
ps
ps
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
MDS 650-12 A
3
Revision 113000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com





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