System Clock. ICS650R-14B Datasheet

ICS650R-14B Clock. Datasheet pdf. Equivalent


Integrated Circuit Systems ICS650R-14B
( DataSheet : www.DataSheet4U.com )
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Description
The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
all have 0 ppm synthesis error.
Block Diagram
Features
• Packaged in 20 pin (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• One fixed output clock of one 25.0 MHz
• One bank of four frequency selectable
output clocks
• Three frequency selectable clock outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
• Industrial temperature range available
2
SELA 0:1
SELB 0:1 2
SELC
VDD GND
22
Clock Synthesis
and Control
Circuitry
25.00 MHz
crystal or clock
X1/ICLK
X2
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
4
Output
Buffer
Output
Buffer
Output
Buffer
CLKA 1:4
CLKA5
CLKB
CLKC
Output
Buffer
25.00 MHz
OE (All outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MDS 650-14B A
1
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
www.DataSheet4U.com


ICS650R-14B Datasheet
Recommendation ICS650R-14B Datasheet
Part ICS650R-14B
Description Networking System Clock
Feature ICS650R-14B; ( DataSheet : www.DataSheet4U.com ) PRELIMINARY INFORMATION ICS650-14B Networking System Clock De.
Manufacture Integrated Circuit Systems
Datasheet
Download ICS650R-14B Datasheet




Integrated Circuit Systems ICS650R-14B
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Pin Assignment
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
1
2
3
4
5
6
7
8
9
10
20 SELC
19 SELA0
18 CLKA2
17 CLKA3
16 VDD
15 SELA1
14 GND
13 CLKA4
12 CLKA1
11 OE
20 pin (150 mil) SSOP
Pin Descriptions
Table 1
SELA1
0
0
0
M
M
M
1
1
1
SELA0
0
M
1
0
M
1
0
M
1
CLKA1:4
33.33
50
66.67
100
33.33
50
33.33
25
66.67
CLKA5
66.66
75
133.33
33.33
83.33
125
100
75
100
Table 2
SELB1
0
0
0
1
1
1
SELB0
0
M
1
0
M
1
CLKB
30
27
48
83.33
19.44
80
Table 3
SELC
0
M
1
CLKC
CLKB/4
62.5
125
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
OE
CLKA1
CLKA4
GND
SELA1
VDD
CLKA3
CLKA2
SELA0
SELC
Type
TI
XO
XI
P
I(Pu)
P
O
O
O
O
I(Pu)
O
O
P
TI
P
O
O
TI
TI
Description
Select pin for CLKB. See Table 2.
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Select pin for CLK B. See table 2.
Connect to ground.
Selectable clock output. See Table 2.
Selectable clock output. See Table 3.
Selectable clock output. See Table 1.
25.0 MHz clock output.
Output Enable. Tri-states all output clocks when low. Internal pull-up.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Connect to ground.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Connect to +3.3V or +5.0V. Must be same as other VDDs.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Select pin for CLKC output. See Table 3.
Key: XI, XO = crystal connections; I = Input; I(Pu) = Input with pull up O = Output; P = power supply connection; TI = tri level input
MDS 650-14B A
2
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com



Integrated Circuit Systems ICS650R-14B
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
Ambient Operating Temperature
Industrial "I" version
Soldering Temperature
Max of 20 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Clock Input
Input Low Voltage, VIL, X1 pin only
Clock Input
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
IOH=-12mA
Output Low Voltage, VOL
IOL=12mA
Output High Voltage, VOH, CMOS level
IOH=-8mA
Operating Supply Current, IDD
No Load
Short Circuit Current
Each output
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle
At VDD/2
Frequency error
All clocks
Absolute Jitter, short term
Variation from mean
Minimum Typical Maximum Units
7V
-0.5 VDD+0.5 V
0 70 °C
-40 85 °C
260 °C
-65 150 °C
3
VDD/2 + 1
VDD - 0.5
2.0
2.4
VDD-0.4
TBD
±50
5.5
VDD/2 - 1
0.5
0.8
0.4
V
V
V
V
V
V
V
V
V
V
mA
mA
25.000
MHz
1.5 ns
1.5 ns
45 50 55 %
0 ppm
TBD
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
External Components
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and
14, as close to the ICS650R-14B as possible. A series termination resistor of 33 may be used for each
clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should
be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =
(CL-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used.
MDS 650-14B A
3
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com







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