ST24W08. 24W08 Datasheet

24W08 ST24W08. Datasheet pdf. Equivalent

24W08 Datasheet
Recommendation 24W08 Datasheet
Part 24W08
Description ST24W08
Feature 24W08; ST24C08, ST25C08 ST24W08, ST25W08 8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protect.
Manufacture ST Microelectronics
Datasheet
Download 24W08 Datasheet




ST Microelectronics 24W08
ST24C08, ST25C08
ST24W08, ST25W08
8 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x08 versions
– 2.5V to 5.5V for ST25x08 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W08 and ST25W08
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES)
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 8 Kbits I2C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control ver-
sion.
Table 1. Signal Names
PRE
E
SDA
SCL
MODE
WC
VCC
VSS
Write Protect Enable
Chip Enable Input
Serial Data Address Input/Output
Serial Clock
Multibyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
E
PRE
SCL
MODE/WC*
ST24x08
ST25x08
SDA
VSS
AI00860E
Note: WC signal is only available for ST24/25W08 products.
February 1999
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ST Microelectronics 24W08
ST24/25C08, ST24/25W08
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x08
ST25x08
PRE 1
NC 2
8 VCC
7 MODE/WC
E3
6 SCL
VSS 4
5 SDA
AI00861E
PRE
NC
E
VSS
ST24x08
ST25x08
18
27
36
45
AI01073E
VCC
MODE/WC
SCL
SDA
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
–40 to 125
°C
TSTG Storage Temperature
–65 to 150
°C
TLEAD Lead Temperature, Soldering
(SO8 package)
40 sec
(PSDIP8 package) 10 sec
215
260
°C
VIO Input or Output Voltages
–0.6 to 6.5
V
VCC Supply Voltage
–0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
4000
500
V
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 ).
3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont’d)
The ST24/25x08 are 8 Kbit electrically erasable
programmable memories (EEPROM), organized
as 4 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
ance of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus defini-
tion. This is used together with 1 chip enable input
(E) so that up to 2 x 8K devices may be attached
to the I2C bus and selected individually. The memo-
ries behave as a slave device in the I2C protocol
with all memory operations synchronized by the
serial clock. Read and write operations are initiated
by a START condition generated by the bus master.
The START condition is followed by a stream of 7
bits (identification code 1010), plus one read/write
bit and terminated by an acknowledge bit.
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ST Microelectronics 24W08
Table 3. Device Select Code
Device Code
Bit b7 b6 b5
Device Select
101
Note: The MSB b7 is sent first.
ST24/25C08, ST24/25W08
Chip
Enable
Block
Select
b4 b3 b2 b1
0 E A9 A8
RW
b0
RW
Table 4. Operating Modes (1)
Mode
Current Address Read
RW bit
’1’
MODE
X
Random Address Read
’0’
’1’
X
Sequential Read
’1’ X
Byte Write
Multibyte Write (2)
’0’ X
’0’ VIH
Page Write
’0’ VIL
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W08 versions.
Bytes
1
1
1 to 1024
1
8
16
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E). This chip enable input is used to
set one least significant bit (b3) of the device select
byte code. This input may be driven dynamically or
tied to VCC or VSS to establish the device select
code.
Protect Enable (PRE). The PRE input pin, in ad-
dition to the status of the Block Address Pointer bit
(b2, location 3FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as a VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
(WC) feature is offered only for ST24W08 and
ST25W08 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory area is not write protected.
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