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Processor Core. MIPS324KEP Datasheet

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Processor Core. MIPS324KEP Datasheet






MIPS324KEP Core. Datasheet pdf. Equivalent




MIPS324KEP Core. Datasheet pdf. Equivalent





Part

MIPS324KEP

Description

Processor Core



Feature


( DataSheet : www.DataSheet4U.com ) MIP S32™ 4KEp™ Processor Core Datasheet November 8, 2002 The MIPS32™ 4KEp core from MIPS® Technologies is a m ember of the MIPS32 4KE™ processor co re family. It is a high-performance, lo w-power, 32-bit MIPS RISC core designed for custom system-on-silicon applicati ons. The core is designed for semicondu ctor manufacturing companies,.
Manufacture

MIPS Technologies

Datasheet
Download MIPS324KEP Datasheet


MIPS Technologies MIPS324KEP

MIPS324KEP; ASIC developers, and system OEMs who wa nt to rapidly integrate their own custo m logic and peripherals with a high-per formance RISC processor. It is highly p ortable across processes, and can be ea sily integrated into full system-on-sil icon designs, allowing developers to fo cus their attention on end-user product s. The 4KEp core is ideally positioned to support new pro.


MIPS Technologies MIPS324KEP

ducts for emerging segments of the digit al consumer, network, systems, and info rmation management markets, enabling ne w tailored solutions for embedded appli cations. The 4KEp core implements the M IPS32 Release 2 Architecture with the M IPS16e™ ASE, and the 32-bit privilege d resource architecture. The Memory Man agement Unit (MMU) consists of a simple , Fixed Mapping Tran.


MIPS Technologies MIPS324KEP

slation (FMT) mechanism for applications that do not require the full capabilit ies of a Translation Lookaside Buffer- (TLB-) based MMU. Instruction and data caches are fully configurable from 0 - 64 Kbytes in size. In addition, each c ache can be organized as direct-mapped or 2-way, 3-way, or 4-way set associati ve. Load and fetch cache misses only bl ock until the critic.

Part

MIPS324KEP

Description

Processor Core



Feature


( DataSheet : www.DataSheet4U.com ) MIP S32™ 4KEp™ Processor Core Datasheet November 8, 2002 The MIPS32™ 4KEp core from MIPS® Technologies is a m ember of the MIPS32 4KE™ processor co re family. It is a high-performance, lo w-power, 32-bit MIPS RISC core designed for custom system-on-silicon applicati ons. The core is designed for semicondu ctor manufacturing companies,.
Manufacture

MIPS Technologies

Datasheet
Download MIPS324KEP Datasheet




 MIPS324KEP
( DataSheet : www.DataSheet4U.com )
MIPS32™ 4KEp™ Processor Core Datasheet
November 8, 2002
The MIPS32™ 4KEp™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a
high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is
designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate
their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and
can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user
products. The 4KEp core is ideally positioned to support new products for emerging segments of the digital consumer,
network, systems, and information management markets, enabling new tailored solutions for embedded applications.
The 4KEp core implements the MIPS32 Release 2 Architecture with the MIPS16e™ ASE, and the 32-bit privileged
resource architecture. The Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT)
mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer- (TLB-) based MMU.
Instruction and data caches are fully configurable from 0 - 64 Kbytes in size. In addition, each cache can be organized as
direct-mapped or 2-way, 3-way, or 4-way set associative. Load and fetch cache misses only block until the critical word
becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches
are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated.
An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data
virtual address/value breakpoints. Additionally, real-time tracing of instruction program counter, data address, and data
values can be supported.
Figure 1 shows a block diagram of the 4KEp core. The core is divided into required and optional blocks as shown.
MDU
I-cache
EJTAG
Trace
TAP
Off/On-Chip
Trace I/F
Off-Chip
Debug I/F
UDI Execution
Core
(RF/ALU/Shift)
CP2
System
Coprocessor
MMU
FMT
Cache
Controller
BIU
D-cache
Power
Mgmt
On-Chip
Coprocessor 2
Fixed/Required
Optional
Figure 1 4KEp Core Block Diagram
MIPS32™ 4KEp™ Processor Core Datasheet, Revision 02.00
Document Number: MD00113
Copyright © 2001-2002 MIPS Technologies Inc. All rights reserved.
www.DataSheet4U.com




 MIPS324KEP
Features
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32-Compatible Instruction Set
– Multiply-Accumulate and Multiply-Subtract
Instructions (MADD, MADDU, MSUB, MSUBU)
– Targeted Multiply Instruction (MUL)
– Zero/One Detect Instructions (CLZ, CLO)
– Wait Instruction (WAIT)
– Conditional Move Instructions (MOVZ, MOVN)
– Prefetch Instruction (PREF)
• MIPS32 Enhanced Architecture (Release 2) Features
– Vectored interrupts and support for external interrupt
controller
– Programmable exception vector base
– Atomic interrupt enable/disable
– GPR shadow registers (optionally, one or three
additional shadows can be added to minimize latency
for interrupt handlers)
– Bit field manipulation instructions
• MIPS16e™ Code Compression
– 16 bit encodings of 32 bit instructions to improve code
density
– Special PC-relative instructions for efficient loading of
addresses and constants
– SAVE & RESTORE macro instructions for setting up
and tearing down stack frames within subroutines
– Improved support for handling 8 and 16 bit datatypes
• Programmable Cache Sizes
– Individually configurable instruction and data caches
– Sizes from 0 - 64KB
– Direct Mapped, 2-, 3-, or 4-Way Set Associative
– Loads block only until critical word is available
– Write-back and write-through support
– 16-byte cache line size
– Virtually indexed, physically tagged
– Cache line locking support
– Non-blocking prefetches
• Scratchpad RAM Support
– Can optionally replace 1 way of the I- and/or D-cache
with a fast scratchpad RAM
– Independent external pin interfaces for I- and D-
scratchpads
– 20 index address bits allow access of arrays up to 1MB
– Interface allows back-stalling the core
• MIPS32 Privileged Resource Architecture
– Count/Compare registers for real-time timer interrupts
– I and D watch registers for SW breakpoints
• Memory Management Unit
– Simple Fixed Mapping Translation (FMT) mechanism
• Simple Bus Interface Unit (BIU)
– All I/O’s fully registered
– Separate unidirectional 32-bit address and data buses
– Two 16-byte collapsing write buffers
– Designed to allow easy conversion to other bus
protocols
• CorExtend™ User Defined Instruction Set Extensions
(available in 4KEp Pro™ core)
– Allows user to define and add instructions to the core at
build time
– Maintains full MIPS32 compatibility
– Supported by industry standard development tools
– Single or multi-cycle instructions
– Separately licensed; a core with this feature is known as
the 4KEp Pro™ core
• Multiply/Divide Unit
– 32 clock latency on multiply
– 34 clock latency on multiply-accumulate
– 33-35 clock latency on divide (sign-dependent)
• Coprocessor 2 interface
– 32 bit interface to an external coprocessor
• Power Control
– Minimum frequency: 0 MHz
– Power-down mode (triggered by WAIT instruction)
– Support for software-controlled clock divider
– Support for extensive use of local gated clocks
• EJTAG Debug
– Support for single stepping
– Virtual instruction and data address/value breakpoints
– PC and data tracing
– TAP controller is chainable for multi-CPU debug
– Cross-CPU breakpoint support
• Testability
– Full scan design achieves test coverage in excess of
99% (dependent on library and configuration options)
– Optional memory BIST for internal SRAM arrays
Architecture Overview
The 4KEp core contains both required and optional blocks.
Required blocks are the lightly shaded areas of the block
diagram in Figure 1 and must be implemented to remain
MIPS-compliant. Optional blocks can be added to the
4KEp core based on the needs of the implementation.
The required blocks are as follows:
• Execution Unit
2 MIPS32™ 4KEp™ Processor Core Datasheet, Revision 02.00
Copyright © 2001-2002 MIPS Technologies Inc. All rights reserved.




 MIPS324KEP
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Memory Management Unit (MMU)
• Fixed Mapping Translation (FMT)
• Cache Controllers
• Bus Interface Unit (BIU)
• Power Management
Optional blocks include:
• Instruction Cache
• Data Cache
• Scratchpad RAM interface
• Coprocessor 2 interface
• CorExtend™ User Defined Instruction (UDI) support
• MIPS16e support
• Enhanced JTAG (EJTAG) Controller
The section entitled "4KEp Core Required Logic Blocks"
on page 4 discusses the required blocks. The section
entitled "4KEp Core Optional Logic Blocks" on page 11
discusses the optional blocks.
Pipeline Flow
The 4KEp core implements a 5-stage pipeline with
performance similar to the R3000® pipeline. The pipeline
allows the processor to achieve high frequency while
minimizing device complexity, reducing both cost and
power consumption.
The 4KEp core pipeline consists of five stages:
• Instruction (I Stage)
• Execution (E Stage)
• Memory (M Stage)
• Align (A Stage)
• Writeback (W stage)
The 4KEp core implements a bypass mechanism that
allows the result of an operation to be forwarded directly to
the instruction that needs it without having to write the
result to the register and then read it back.
Figure 2 shows a timing diagram of the 4KEp core pipeline.
I
I-Cache
EM
Bypass
Bypass
RegRd
ALU Op
I Dec D-AC D-Cache
A
Align
I-A1 I-A2
MUL
mul, div
RegW
W
RegW
RegW
Figure 2 4KEp Core Pipeline
I Stage: Instruction Fetch
During the Instruction fetch stage:
• An instruction is fetched from instruction cache.
• MIPS16e instructions are expanded into MIPS32-like
instructions
E Stage: Execution
During the Execution stage:
• Operands are fetched from register file.
• The arithmetic logic unit (ALU) begins the arithmetic
or logical operation for register-to-register instructions.
• The ALU calculates the data virtual address for load
and store instructions.
• The ALU determines whether the branch condition is
true and calculates the virtual branch target address for
branch instructions.
• Instruction logic selects an instruction address.
• All multiply and divide operations begin in this stage.
M Stage: Memory Fetch
During the Memory fetch stage:
• The arithmetic ALU operation completes.
• The data cache access and the data virtual-to-physical
address translation are performed for load and store
instructions.
• Data cache look-up is performed and a hit/miss
determination is made.
• A multiply operation stalls the MDU pipeline for 31
clocks in the M stage.
MIPS32™ 4KEp™ Processor Core Datasheet, Revision 02.00
Copyright © 2001-2002 MIPS Technologies Inc. All rights reserved.
3






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