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STP50NE10L. P50NE10L Datasheet

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STP50NE10L. P50NE10L Datasheet







P50NE10L STP50NE10L. Datasheet pdf. Equivalent




P50NE10L STP50NE10L. Datasheet pdf. Equivalent





Part

P50NE10L

Description

STP50NE10L

Manufacture

ST Microelectronics

Datasheet
Download P50NE10L Datasheet


ST Microelectronics P50NE10L

P50NE10L; www.DataSheet4U.com s s s s s m o .c U 4 t e STP50NE10L e h S N - CHANNEL 100V - 0.020Ω - 50A TO-220 a t STripFET POWER MOSFET a .D w w w TYPICAL R = 0 .020 Ω ® TYPE VDSS R DS(on) ID STP50 NE10L 100 V <0.025 Ω 50 A EXCEPTIONA L dv/dt CAPABILITY 100% AVALANCHE TESTE D LOW GATE CHARGE AT 100 oC APPLICATION ORIENTED CHARACTERIZATION DESCRIPTION This Power MOSFET is the l.


ST Microelectronics P50NE10L

atest development of STMicroelectronics unique "Single Feature Size™" strip-b ased process. The resulting transistor shows extremely high packing density fo r low on-resistance, rugged avalanche c haracteristics and less critical alignm ent steps therefore a remarkable manufa cturing reproducibility. APPLICATIONS H IGH CURRENT, HIGH SPEED SWITCHING s SOL ENOID AND RELAY DRIV.


ST Microelectronics P50NE10L

ERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s AUTOMOTIVE E NVIRONMENT (INJECTION, ABS, AIR-BAG, LA MPDRIVERS, Etc.) s ABSOLUTE MAXIMUM RA TINGS Symbol V DS V DGR V GS ID ID I DM (• ) P tot Drain-source Voltage (V GS = 0) Gate-source Voltage Drain- gat e Voltage (R GS = 20 k Ω ) Drain Cur rent (continuous) at T c = 25 C o m o .c U 4 t e e h S a t a.



Part

P50NE10L

Description

STP50NE10L

Manufacture

ST Microelectronics

Datasheet
Download P50NE10L Datasheet




 P50NE10L
eet4U.com® STP50NE10L
Sh N - CHANNEL 100V - 0.020- 50A TO-220
ata STripFETPOWER MOSFET
w.DTYPE
VDSS
RDS(on)
w STP50NE10L
100 V <0.025
wwww.DataSheet4Us.comTYPICAL RDS(on) = 0.020
ID
50 A
s EXCEPTIONAL dv/dt CAPABILITY
s 100% AVALANCHE TESTED
ms LOW GATE CHARGE AT 100 oC
s APPLICATION ORIENTED
oCHARACTERIZATION
.cDESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique "Single Feature
USize" strip-based process. The resulting
t4transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
etherefore a remarkable manufacturing
ereproducibility.
hAPPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
Ss SOLENOID AND RELAY DRIVERS
s MOTOR CONTROL, AUDIO AMPLIFIERS
tas DC-DC & DC-AC CONVERTERS
s AUTOMOTIVE ENVIRONMENT (INJECTION,
aABS, AIR-BAG, LAMPDRIVERS, Etc.)
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
.DABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
wVDS Drain-source Voltage (VGS = 0)
wVDGR Drain- gate Voltage (RGS = 20 k)
VGS
wID
mID
oIDM()
.cPtot
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
Drain Current (pulsed)
Total Dissipation at Tc = 25 oC
t4UDerating Factor
edv/dt (1) Peak Diode Recovery voltage slope
eTstg Storage Temperature
hTj Max. Operating Junction Temperature
taS() Pulse width limited by safe operating area
www.DaMay 1999
Value
Unit
100 V
100 V
± 20
V
50 A
35 A
200 A
150 W
1 W/oC
6 V/ns
-65 to 175
oC
175 oC
(1) ISD 50 A, di/dt 275 A/µs, VDD V(BR)DSS, Tj TJMAX
1/8





 P50NE10L
STP50NE10L
THERMAL DATA
Rthj-case
Rthj-amb
Rthc-sink
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
Typ
Maximum Lead Temperature For Soldering Purpose
1
62.5
0.5
300
oC/W
oC/W
oC/W
oC
AVALANCHE CHARACTERISTICS
Symbol
IAR
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EAS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
Single Pulse Avalanche Energy
(starting Tj = 25 oC, ID = IAR, VDD = 50 V)
Max Value
50
400
Unit
A
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbol
V(BR)DSS
IDSS
IGSS
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA VGS = 0
Zero Gate Voltage
VDS = Max Rating
Drain Current (VGS = 0) VDS = Max Rating
Tc = 125 oC
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V
Min.
100
Typ.
Max.
Unit
V
1
10
± 100
µA
µA
nA
ON ()
Symbol
VGS(th)
RDS(on)
ID(on)
Parameter
Test Conditions
Gate Threshold Voltage VDS = VGS ID = 250 µA
Static Drain-source On VGS = 10 V ID = 25 A
Resistance
VGS = 5 V ID = 25 A
On State Drain Current VDS > ID(on) x RDS(on)max
VGS = 10 V
Min.
1
50
Typ.
1.7
0.020
0.024
Max.
2.5
0.025
0.030
Unit
V
A
DYNAMIC
Symbol
gfs ()
Ciss
Coss
Crss
Parameter
Forward
Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
VDS > ID(on) x RDS(on)max ID =25 A
VDS = 25 V f = 1 MHz VGS = 0
Min.
Typ.
45
Max.
Unit
S
5000
500
180
pF
pF
pF
2/8





 P50NE10L
STP50NE10L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
td(on)
tr
Parameter
Turn-on Delay Time
Rise Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
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SWITCHING OFF
Test Conditions
VDD = 50 V
ID = 25 A
RG = 4.7
VGS = 5 V
(Resistive Load, see fig. 3)
VDD = 80 V ID = 50 A VGS = 5 V
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 50 V
ID = 25 A
RG = 4.7
VGS = 5 V
(Resistive Load, see fig. 3)
Vclamp = 80 V
ID = 50 A
RG = 4.7 Ω
VGS = 5 V
(Inductive Load, see fig. 5)
Min.
Min.
Typ.
30
105
82
17
49
Typ.
135
45
45
45
85
Max.
105
Max.
Unit
ns
ns
nC
nC
nC
Unit
ns
ns
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD
ISDM()
Source-drain Current
Source-drain Current
(pulsed)
VSD () Forward On Voltage
ISD = 50 A VGS = 0
trr
Qrr
IRRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD = 30 A
VDD = 50 V
di/dt = 100 A/µs
Tj = 150 oC
(see test circuit, fig. 5)
() Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
() Pulse width limited by safe operating area
Min.
Typ.
165
870
10.5
Max.
50
200
1.5
Unit
A
A
V
ns
nC
A
Safe Operating Area
Thermal Impedance
3/8



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