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4 bits. EDD2504AKTA-E Datasheet

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4 bits. EDD2504AKTA-E Datasheet






EDD2504AKTA-E bits. Datasheet pdf. Equivalent




EDD2504AKTA-E bits. Datasheet pdf. Equivalent





Part

EDD2504AKTA-E

Description

256M bits DDR SDRAM (64M words x 4 bits)



Feature


( DataSheet : www.DataSheet4U.com ) DAT A SHEET 256M bits DDR SDRAM EDD2504AKT A-E (64M words × 4 bits) Description T he EDD2504AKTA is a 256M bits Double Da ta Rate (DDR) SDRAM organized as 16,777 ,216 words × 4 bits × 4 banks. Read a nd write operations are performed at th e cross points of the CK and the /CK. T his highspeed data transfer is realized by the 2 bits prefet.
Manufacture

Elpida Memory

Datasheet
Download EDD2504AKTA-E Datasheet


Elpida Memory EDD2504AKTA-E

EDD2504AKTA-E; chpipelined architecture. Data strobe (D QS) both for read and write are availab le for high speed and reliable data bus design. By setting extended mode regis ter, the on-chip Delay Locked Loop (DLL ) can be set enable or disable. It is p ackaged in 66-pin plastic TSOP (II). P in Configurations /xxx indicates active low signal. 66-pin Plastic TSOP(II) VD D NC VDDQ NC DQ0 V.


Elpida Memory EDD2504AKTA-E

SSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) Features • Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0 .2V • Data rate: 333Mbps/266Mbps (max .) • Double Data Rate architecture; t wo data transfers per cloc.


Elpida Memory EDD2504AKTA-E

k cycle • Bi-directional, data strobe (DQS) is transmitted /received with dat a, to be used in capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • 4 inte rnal banks for concurrent operation • DQS is edge aligned with data for READ s; center aligned with data for WRITEs • Differential clock inputs (CK and / CK) • DLL aligns DQ and DQS .

Part

EDD2504AKTA-E

Description

256M bits DDR SDRAM (64M words x 4 bits)



Feature


( DataSheet : www.DataSheet4U.com ) DAT A SHEET 256M bits DDR SDRAM EDD2504AKT A-E (64M words × 4 bits) Description T he EDD2504AKTA is a 256M bits Double Da ta Rate (DDR) SDRAM organized as 16,777 ,216 words × 4 bits × 4 banks. Read a nd write operations are performed at th e cross points of the CK and the /CK. T his highspeed data transfer is realized by the 2 bits prefet.
Manufacture

Elpida Memory

Datasheet
Download EDD2504AKTA-E Datasheet




 EDD2504AKTA-E
( DataSheet : www.DataSheet4U.com )
DATA SHEET
256M bits DDR SDRAM
EDD2504AKTA-E (64M words × 4 bits)
Description
The EDD2504AKTA is a 256M bits Double Data Rate
(DDR) SDRAM organized as 16,777,216 words × 4 bits
× 4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 66-pin plastic
TSOP (II).
Features
Power supply : VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
Pin Configurations
/xxx indicates active low signal.
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
66-pin Plastic TSOP(II)
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ3
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0610E10 (Ver. 1.0)
Date Published November 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
www.DataSheet4U.com




 EDD2504AKTA-E
EDD2504AKTA-E
Ordering Information
Part number
EDD2504AKTA-6B-E
EDD2504AKTA-7A-E
EDD2504AKTA-7B-E
Mask
version
K
Organization
(words × bits)
64M × 4
Internal
banks
4
Data rate
Mbps (max.)
333
266
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR-333B (2.5-3-3)
DDR-266A (2-3-3)
DDR-266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 25 04 A K TA - 6B - E
Elpida Memory
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Bit Organization
4: x4
Voltage, Interface
A: 2.5V, SSTL_2
Die Rev.
Environment Code
E: Lead Free
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Package
TA: TSOP (II)
Data Sheet E0610E10 (Ver. 1.0)
2




 EDD2504AKTA-E
EDD2504AKTA-E
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Data Sheet E0610E10 (Ver. 1.0)
3






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