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bits DDR400. EDD2516AKTA-E Datasheet

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bits DDR400. EDD2516AKTA-E Datasheet







EDD2516AKTA-E DDR400. Datasheet pdf. Equivalent




EDD2516AKTA-E DDR400. Datasheet pdf. Equivalent





Part

EDD2516AKTA-E

Description

256M bits DDR SDRAM (16M words x16 bits DDR400)

Manufacture

Elpida Memory

Datasheet
Download EDD2516AKTA-E Datasheet


Elpida Memory EDD2516AKTA-E

EDD2516AKTA-E; ( DataSheet : www.DataSheet4U.com ) DAT A SHEET 256M bits DDR SDRAM EDD2516AKT A-E (16M words × 16 bits) Description The EDD2516AKTA is a 256M bits Double D ata Rate (DDR) SDRAM organized as 4,194 ,304 words × 16 bits × 4 banks. Read and write operations are performed at t he cross points of the CK and the /CK. This highspeed data transfer is realize d by the 2 bits prefe.


Elpida Memory EDD2516AKTA-E

tchpipelined architecture. Data strobe ( DQS) both for read and write are availa ble for high speed and reliable data bu s design. By setting extended mode regi ster, the on-chip Delay Locked Loop (DL L) can be set enable or disable. It is packaged in 66-pin plastic TSOP (II). Pin Configurations /xxx indicates activ e low signal. 66-pin Plastic TSOP(II) V DD DQ0 VDDQ DQ1 DQ.


Elpida Memory EDD2516AKTA-E

2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS / CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD Features • Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.) • Double Data Rate architecture; two data trans fers per clock cycle • Bi-directional , data strobe (DQS) is transmitted /rec eived with data, to be used .



Part

EDD2516AKTA-E

Description

256M bits DDR SDRAM (16M words x16 bits DDR400)

Manufacture

Elpida Memory

Datasheet
Download EDD2516AKTA-E Datasheet




 EDD2516AKTA-E
( DataSheet : www.DataSheet4U.com )
DATA SHEET
256M bits DDR SDRAM
EDD2516AKTA-E (16M words × 16 bits)
Description
The EDD2516AKTA is a 256M bits Double Data Rate
(DDR) SDRAM organized as 4,194,304 words × 16 bits
× 4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 66-pin plastic
TSOP (II).
Features
Power supply : VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
RoHS compliant
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0502E30 (Ver. 3.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
www.DataSheet4U.com





 EDD2516AKTA-E
EDD2516AKTA-E
Ordering Information
Part number
EDD2516AKTA-6B-E
EDD2516AKTA-7A-E
EDD2516AKTA-7B-E
Mask
version
K
Organization
(words × bits)
16M × 16
Internal
banks
4
Data rate
Mbps (max.)
333
266
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR-333B (2.5-3-3)
DDR-266A (2-3-3)
DDR-266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 25 16 A K TA - 6B - E
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Organization
16: x16
Power Supply, Interface
A: 2.5V, SSTL_2
Environment Code
E: Lead Free
Package
TA: TSOP (II)
Die Rev.
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Data Sheet E0502E30 (Ver. 3.0)
2





 EDD2516AKTA-E
EDD2516AKTA-E
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Data Sheet E0502E30 (Ver. 3.0)
3



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