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Freescale Semiconductor Data Sheet
MCF5213EC Rev. 0, 05/2005
MCF5213 Microcontroller Family Hardware Specification
The MCF5213 is a member of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This hardware specification provides an overview of the 32-bit MCF5213 microcontroller, focusing on its highly integrated and diverse feature set. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM). On-chip modules include the following: • V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal Flash with Multiply Accumulate (MAC) Unit and hardware divider • FlexCAN controller area network (CAN) module • Three universal asynchronous/synchronous receiver/transmitters (UARTs)
Table of Contents
1 MCF5213 Family Configurations .........................2 1.1 Block Diagram ...................................................3 1.2 Features.............................................................4 1.3 Part Numbers and Packaging..........................14 1.4 Package Pinouts..............................................15 1.5 Reset Signals ..................................................20 1.6 PLL and Clock Signals ....................................20 1.7 Mode Selection................................................21 1.8 External Interrupt Signals ................................21 1.9 Queued Serial Peripheral Interface (QSPI) .....22 1.10 I2C I/O Signals.................................................22 1.11 UART Module Signals .....................................22 1.12 DMA Timer Signals..........................................23 1.15 Pulse Width Modulator Signals........................24 1.16 Debug Support Signals....................................24 1.17 EzPort Signal Descriptions ..............................26 1.18 Power and Ground Pins...................................26 2 3 Preliminary Electrical Characteristics................26 Mechanical Outline Drawings ............................42
This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved.
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MCF5213 Family Configurations
• • • • • • • • • • • •
Inter-integrated circuit (I2C™) bus controller Queued serial peripheral interface (QSPI) module Eight-channel 12-bit fast analog-to-digital converter (ADC) Four-channel direct memory access (DMA) controller Four 32-bit input capture/output compare timers with DMA support (DTIM) Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer Two 16-bit periodic interrupt timers (PITs) Programmable software watchdog timer Interrupt controller capable of handling 63 selectable-priority interrupt sources Clock module with 8 MHz on-chip relaxation oscillator and integrated phase locked loop (PLL) Test access/debug port (JTAG, BDM)
1
MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations
Module ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash / Static RAM (SRAM) Interrupt Controller (INTC) Fast Analog-to-Digital Converter (ADC) FlexCAN 2.0B Module Four-channel Direct-Memory Access (DMA) Software Watchdog Timer (WDT) Programmable Interrupt Timer Four-Channel General Purpose Timer 32-bit DMA Timers QSPI UART(s) I2C Eight/Four-channel 8/16-bit PWM Timer General Purpose I/O Module (GPIO) 5211 x 66 MHz 63 128/16 Kbytes x x x x 2 x 4 x 3 x x x x x x x 2 x 4 x 3 x x x 5212 x 66, 80 MHz up to 76 256/32 Kbytes x x x x x 2 x 4 x 3 x x x 5213 x
MCF5213 Microcontroller Family Hardware Specification, Rev. 0 2 Freescale Semiconductor
MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations (continued)
Module Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port Package NOTES:
1 1
5211 x x x
5212 x x x
5213 x x x
64-pin LQFP 64-pin LQFP 81-ball MAPBGA 81-ball MAPBGA 81-ball MAPBGA 100-Lead LQFP
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller packages.
1.1
Block Diagram
The MCF5213 comes in a 100-pin low-profile quad flat pack (LQFP) and operates in single-chip mode only. Figure 1 shows a top-level block diagram of the MCF5213. Other members of this family can have different package options, which are described later in this .