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TRI-STATE Outputs. 54F244 Datasheet

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TRI-STATE Outputs. 54F244 Datasheet







54F244 Outputs. Datasheet pdf. Equivalent




54F244 Outputs. Datasheet pdf. Equivalent





Part

54F244

Description

(54F240 - 54F244) Octal Buffers/Line Drivers with TRI-STATE Outputs

Manufacture

National Semiconductor

Datasheet
Download 54F244 Datasheet


National Semiconductor 54F244

54F244; 54F 74F24054F 74F24154F 74F244 Octal B uffers Line Drivers with TRI-STATE Outp uts Obsolete May 1995 54F 74F24054F 74F24154F 74F244 Octal Buffers Line D rivers with TRI-STATE Outputs General Description The ’F240 ’F241 and ’ F244 are octal buffers and line drivers designed to be employed as memory and address drivers clock drivers and bus-o riented transmitters rec.


National Semiconductor 54F244

eivers which provide improved PC and boa rd density Features Y TRI-STATE output s drive bus lines or buffer memory addr ess registers Y Outputs sink 64 mA (48 mA mil) Y 12 mA source current Y Input clamp diodes limit high-speed terminati on effects Y Guaranteed 4000V minimum E SD protection Commercial 74F240PC 74F2 40SC (Note 1) 74F240SJ (Note 1) 74F241P C 74F241SC (Note 1.


National Semiconductor 54F244

) 74F241SJ (Note 1) 74F244PC 74F244SC (N ote 1) 74F244SJ (Note 1) 74F244MSA (Not e 1) Military 54F240DM (Note 2) 54F240 FM (Note 2) 54F240LM (Note 2) 54F241DM (Note 2) 54F241FM (Note 2) 54F241LM (No te 2) 54F244DM (Note 2) 54F244FM (Note 2) 54F244LM (Note 2) Package Number N2 0A J20A M20B M20D W20A E20A N20A J20A M 20B M20D W20A E20A N20A J20A M20B M20D MSA20 W20A E20A P.



Part

54F244

Description

(54F240 - 54F244) Octal Buffers/Line Drivers with TRI-STATE Outputs

Manufacture

National Semiconductor

Datasheet
Download 54F244 Datasheet




 54F244
May 1995
54F 74F24054F 74F24154F 74F244
Octal Buffers Line Drivers with TRI-STATE Outputs
General Description
The ’F240 ’F241 and ’F244 are octal buffers and line driv-
ers designed to be employed as memory and address driv-
ers clock drivers and bus-oriented transmitters receivers
which provide improved PC and board density
Features
Y TRI-STATE outputs drive bus lines or buffer memory
address registers
Y Outputs sink 64 mA (48 mA mil)
Y 12 mA source current
Y Input clamp diodes limit high-speed termination effects
Y Guaranteed 4000V minimum ESD protection
Commercial
74F240PC
74F240SC (Note 1)
74F240SJ (Note 1)
74F241PC
74F241SC (Note 1)
74F241SJ (Note 1)
74F244PC
74F244SC (Note 1)
74F244SJ (Note 1)
74F244MSA (Note 1)
Military
54F240DM (Note 2)
54F240FM (Note 2)
54F240LM (Note 2)
54F241DM (Note 2)
54F241FM (Note 2)
54F241LM (Note 2)
54F244DM (Note 2)
54F244FM (Note 2)
54F244LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
N20A
J20A
M20B
M20D
W20A
E20A
N20A
J20A
M20B
M20D
MSA20
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use Suffix e SCX SJX and MSAX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9501
RRD-B30M75 Printed in U S A





 54F244
Connection Diagrams
’F240
Pin Assignment for LCC
’F241
’F244
TL F 9501–2
TL F 9501 – 4
Pin Assignment for DIP SOIC SSOP and Flatpak
TL F 9501 – 6
TL F 9501–1
Logic Symbols
IEEE IEC
’F240
TL F 9501 – 3
IEEE IEC
’F241
TL F 9501 – 5
IEEE IEC
’F244
TL F 9501–7
TL F 9501 – 8
2
TL F 9501 – 9





 54F244
Unit Loading Fan Out
Pin Names
Description
OE1 OE2
OE2
I0 – I7
I0 – I7
O0 – O7 O0 – O7
TRI-STATE Output Enable Input (Active LOW)
TRI-STATE Output Enable Input (Active HIGH)
Inputs (’F240)
Inputs (’F241 ’F244)
Outputs
Worst-case ’F240 enabled ’F241 ’F244 disabled
54F 74F
UL
HIGH LOW
1 0 1 667
1 0 1 667
1 0 1 667
1 0 2 667
600 106 6 (80)
Input IIH IIL
Output IOH IOL
20 mA b1 mA
20 mA b1 mA
20 mA b1 mA
20 mA b1 6 mA
b12 mA 64 mA (48 mA)
Truth Tables
’F240
OE1 D1n O1n OE2 D2n O2n
HXZHXZ
LHL LHL
L LHL LH
’F241
OE1 D1n O1n OE2 D2n O2n
HXZ LXZ
L HHHHH
L LLHLL
’F244
OE1 D1n O1n OE2
HXZH
L HH L
L LL L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
D2n
X
H
L
O2n
Z
H
L
3



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